GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

amd/cezanne: Control DPTC with only Kconfig 

SOC_AMD_COMMON_BLOCK_ACPI_DPTC can be enabled conditionally for any
guybrush boards, similar to .mainboard/google/zork/Kconfig This makes
the value dptc_tablet_mode_enable redundant.

This CL removes dptc_tablet_mode_enable so DPTC is controlled entirely
with the Kconfig value SOC_AMD_COMMON_BLOCK_ACPI_DPTC. This means DPTC
is only included for boards that actually enable it.

BRANCH=none
BUG=b:217911928
TEST=emerge-guybrush coreboot

Signed-off-by: Tim Van Patten <timvp@google.com>
Change-Id: I07f1266fa80a6c9ee4ec3b3ba970a70c6c72fb54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67638
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
This commit is contained in:
Tim Van Patten 2022-09-13 15:34:08 -06:00 committed by Felix Held
parent 54ce4aa98c
commit 9eac097205
2 changed files with 3 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/cezanne/chip.h
View File

@ -86,8 +86,6 @@ struct soc_amd_cezanne_config {
uint32_t telemetry_vddcrsocfull_scale_current_mA;
uint32_t telemetry_vddcrsocoffset;
bool dptc_enable;
/* The array index is the general purpose PCIe clock output number. Values in here
aren't the values written to the register to have the default to be always on. */
enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT];

6
src/soc/amd/cezanne/root_complex.c
View File

@ -186,10 +186,7 @@ static void acipgen_dptci(void)
{
const struct soc_amd_cezanne_config *config = config_of_soc();
if (!config->dptc_enable)
return;
/* DPTC is enabled. Always fill out the default DPTC values. */
/* Normal mode DPTC values. */
struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC,
config->sustained_power_limit_mW,
config->fast_ppt_limit_mW,
@ -200,6 +197,7 @@ static void acipgen_dptci(void)
static void root_complex_fill_ssdt(const struct device *device)
{
acpi_fill_root_complex_tom(device);
if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC))
acipgen_dptci();
}