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soc/intel/adl: Add override skip_cse_sub_part_update() for alderlake 

Check the Alderlake CPU ID to determine if cse sub-paritition update is
required or not.

BUG=b:202143532

Change-Id: Icae21dad56ed4a1edea1f641b3d5bccc3943f831
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59826
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Krishna Prasad Bhat 2021-12-02 10:30:26 +05:30 committed by Tim Wawrzynczak
parent 333edcc7c6
commit 9eb7070bc4
1 changed files with 6 additions and 0 deletions
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6
src/soc/intel/alderlake/romstage/romstage.c
View File

@ -15,6 +15,7 @@
#include <soc/pm.h> #include <soc/pm.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include <soc/soc_chip.h> #include <soc/soc_chip.h>
#include <cpu/intel/cpu_ids.h>
#include <string.h> #include <string.h>
#define FSP_SMBIOS_MEMORY_INFO_GUID \ #define FSP_SMBIOS_MEMORY_INFO_GUID \
@ -23,6 +24,11 @@
0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \
} }
bool skip_cse_sub_part_update(void)
{
return cpu_get_cpuid() != CPUID_ALDERLAKE_A2;
}
/* Save the DIMM information for SMBIOS table 17 */ /* Save the DIMM information for SMBIOS table 17 */
static void save_dimm_info(void) static void save_dimm_info(void)
{ {