GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

drop extra pci access functions. these are exact copies of romcc_io.h. 

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer 2010-04-30 17:44:39 +00:00 committed by Stefan Reinauer
parent ad894c5449
commit 9ec3d38130
2 changed files with 23 additions and 214 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

229
src/northbridge/via/vx800/pci_rawops.h
View File

@ -2,11 +2,11 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2009 One Laptop per Child, Association, Inc. * Copyright (C) 2009 One Laptop per Child, Association, Inc.
* Copyright (C) 2010 coresystems GmbH
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or * the Free Software Foundation; version 2 of the License.
* (at your option) any later version.
* *
* This program is distributed in the hope that it will be useful, * This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of * but WITHOUT ANY WARRANTY; without even the implied warranty of
@ -18,14 +18,11 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef ARCH_I386_PCI_RAWOPS_H #ifndef NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H
# define ARCH_I386_PCI_RAWOPS_H 1 #define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H
#include <stdint.h>
#define PCI_RAWDEV(SEGBUS, DEV, FN) ( \ #include <stdint.h>
(((SEGBUS) & 0xFFF) << 20) | \ #include <arch/romcc_io.h>
(((DEV) & 0x1F) << 15) | \
(((FN) & 0x07) << 12))
struct VIA_PCI_REG_INIT_TABLE { struct VIA_PCI_REG_INIT_TABLE {
u8 ChipRevisionStart; u8 ChipRevisionStart;
@ -38,219 +35,31 @@ struct VIA_PCI_REG_INIT_TABLE {
u8 Value; u8 Value;
}; };
typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */ static void pci_modify_config8(device_t dev, unsigned where, u8 orval, u8 mask)
#warning "FIXME: get rid of this extra copy of pci access functions."
/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
* We don't need to set %fs, and %gs anymore
* Before that We need to use %gs, and leave %fs to other RAM access
*/
static u8 pci_io_rawread_config8(device_t_raw dev, unsigned where)
{ {
unsigned addr; u8 data = pci_read_config8(dev, where);
#if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev >> 4) | where;
#else
addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); //seg == 0
#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
return inb(0xCFC + (addr & 3));
}
#if CONFIG_MMCONF_SUPPORT
static u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where)
{
unsigned addr;
addr = dev | where;
return read8x(addr);
}
#endif
static u8 pci_rawread_config8(device_t_raw dev, unsigned where)
{
#if CONFIG_MMCONF_SUPPORT
return pci_mmio_rawread_config8(dev, where);
#else
return pci_io_rawread_config8(dev, where);
#endif
}
static u16 pci_io_rawread_config16(device_t_raw dev, unsigned where)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev >> 4) | where;
#else
addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
return inw(0xCFC + (addr & 2));
}
#if CONFIG_MMCONF_SUPPORT
static u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where)
{
unsigned addr;
addr = dev | where;
return read16x(addr);
}
#endif
static u16 pci_rawread_config16(device_t_raw dev, unsigned where)
{
#if CONFIG_MMCONF_SUPPORT
return pci_mmio_rawread_config16(dev, where);
#else
return pci_io_rawread_config16(dev, where);
#endif
}
static u32 pci_io_rawread_config32(device_t_raw dev, unsigned where)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev >> 4) | where;
#else
addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
}
#if CONFIG_MMCONF_SUPPORT
static u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where)
{
unsigned addr;
addr = dev | where;
return read32x(addr);
}
#endif
static u32 pci_rawread_config32(device_t_raw dev, unsigned where)
{
#if CONFIG_MMCONF_SUPPORT
return pci_mmio_rawread_config32(dev, where);
#else
return pci_io_rawread_config32(dev, where);
#endif
}
static void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev >> 4) | where;
#else
addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
outb(value, 0xCFC + (addr & 3));
}
#if CONFIG_MMCONF_SUPPORT
static void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
{
unsigned addr;
addr = dev | where;
write8x(addr, value);
}
#endif
static void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
{
#if CONFIG_MMCONF_SUPPORT
pci_mmio_rawwrite_config8(dev, where, value);
#else
pci_io_rawwrite_config8(dev, where, value);
#endif
}
static void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev >> 4) | where;
#else
addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
outw(value, 0xCFC + (addr & 2));
}
#if CONFIG_MMCONF_SUPPORT
static void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where,
u16 value)
{
unsigned addr;
addr = dev | where;
write16x(addr, value);
}
#endif
static void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
{
#if CONFIG_MMCONF_SUPPORT
pci_mmio_rawwrite_config16(dev, where, value);
#else
pci_io_rawwrite_config16(dev, where, value);
#endif
}
static void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
{
unsigned addr;
#if CONFIG_PCI_IO_CFG_EXT == 0
addr = (dev >> 4) | where;
#else
addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
#endif
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
}
#if CONFIG_MMCONF_SUPPORT
static void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
{
unsigned addr;
addr = dev | where;
write32x(addr, value);
}
#endif
static void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
{
#if CONFIG_MMCONF_SUPPORT
pci_mmio_rawwrite_config32(dev, where, value);
#else
pci_io_rawwrite_config32(dev, where, value);
#endif
}
static void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask)
{
u8 data = pci_rawread_config8(dev, where);
data &= (~mask); data &= (~mask);
data |= orval; data |= orval;
pci_rawwrite_config8(dev, where, data); pci_write_config8(dev, where, data);
} }
static void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask) static void pci_modify_config16(device_t dev, unsigned where, u16 orval, u16 mask)
{ {
u16 data = pci_rawread_config16(dev, where); u16 data = pci_read_config16(dev, where);
data &= (~mask); data &= (~mask);
data |= orval; data |= orval;
pci_rawwrite_config16(dev, where, data); pci_write_config16(dev, where, data);
} }
static void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask) static void pci_modify_config32(device_t dev, unsigned where, u32 orval, u32 mask)
{ {
u32 data = pci_rawread_config32(dev, where); u32 data = pci_read_config32(dev, where);
data &= (~mask); data &= (~mask);
data |= orval; data |= orval;
pci_rawwrite_config32(dev, where, data); pci_write_config32(dev, where, data);
} }
static void io_rawmodify_config8(u16 where, u8 orval, u8 mask) static void io_modify_config8(u16 where, u8 orval, u8 mask)
{ {
u8 data = inb(where); u8 data = inb(where);
data &= (~mask); data &= (~mask);
@ -262,7 +71,7 @@ static void via_pci_inittable(u8 chipversion,
const struct VIA_PCI_REG_INIT_TABLE *initdata) const struct VIA_PCI_REG_INIT_TABLE *initdata)
{ {
u8 i = 0; u8 i = 0;
device_t_raw devbxdxfx; device_t devbxdxfx;
for (i = 0;; i++) { for (i = 0;; i++) {
if ((initdata[i].Mask == 0) && (initdata[i].Value == 0) if ((initdata[i].Mask == 0) && (initdata[i].Value == 0)
&& (initdata[i].Bus == 0) && (initdata[i].Bus == 0)
@ -275,9 +84,9 @@ static void via_pci_inittable(u8 chipversion,
if ((chipversion >= initdata[i].ChipRevisionStart) if ((chipversion >= initdata[i].ChipRevisionStart)
&& (chipversion <= initdata[i].ChipRevisionEnd)) { && (chipversion <= initdata[i].ChipRevisionEnd)) {
devbxdxfx = devbxdxfx =
PCI_RAWDEV(initdata[i].Bus, initdata[i].Device, PCI_DEV(initdata[i].Bus, initdata[i].Device,
initdata[i].Function); initdata[i].Function);
pci_rawmodify_config8(devbxdxfx, pci_modify_config8(devbxdxfx,
initdata[i].Register, initdata[i].Register,
initdata[i].Value, initdata[i].Value,
initdata[i].Mask); initdata[i].Mask);

6
src/northbridge/via/vx800/uma_ram_setting.c
View File

@ -173,10 +173,10 @@ void SetUMARam(void)
pci_write_config32(vga_dev, 0x14, Tmp); pci_write_config32(vga_dev, 0x14, Tmp);
//enable direct cpu frame buffer access //enable direct cpu frame buffer access
i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1); i = pci_read_config8(PCI_DEV(0, 0, 3), 0xa1);
i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28); i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28);
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i); pci_write_config8(PCI_DEV(0, 0, 3), 0xa1, i);
pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01); pci_write_config8(PCI_DEV(0, 0, 3), 0xa0, 0x01);
//enable GFx memory space access control for S.L and mmio //enable GFx memory space access control for S.L and mmio
ByteVal = pci_read_config8(d0f0_dev, 0xD4); ByteVal = pci_read_config8(d0f0_dev, 0xD4);