drop extra pci access functions. these are exact copies of romcc_io.h.
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
Stefan Reinauer
parent
ad894c5449
commit
9ec3d38130
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@ -2,11 +2,11 @@
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2009 One Laptop per Child, Association, Inc.
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* Copyright (C) 2010 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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@ -18,14 +18,11 @@
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef ARCH_I386_PCI_RAWOPS_H
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# define ARCH_I386_PCI_RAWOPS_H 1
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#include <stdint.h>
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#ifndef NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H
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#define NORTHBRIDGE_VIA_VX800_PCI_RAWOPS_H
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#define PCI_RAWDEV(SEGBUS, DEV, FN) ( \
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(((SEGBUS) & 0xFFF) << 20) | \
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(((DEV) & 0x1F) << 15) | \
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(((FN) & 0x07) << 12))
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#include <stdint.h>
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#include <arch/romcc_io.h>
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struct VIA_PCI_REG_INIT_TABLE {
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u8 ChipRevisionStart;
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@ -38,219 +35,31 @@ struct VIA_PCI_REG_INIT_TABLE {
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u8 Value;
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};
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typedef unsigned device_t_raw; /* pci and pci_mmio need to have different ways to have dev */
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#warning "FIXME: get rid of this extra copy of pci access functions."
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/* FIXME: We need to make the coreboot to run at 64bit mode, So when read/write memory above 4G,
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* We don't need to set %fs, and %gs anymore
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* Before that We need to use %gs, and leave %fs to other RAM access
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*/
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static u8 pci_io_rawread_config8(device_t_raw dev, unsigned where)
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static void pci_modify_config8(device_t dev, unsigned where, u8 orval, u8 mask)
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{
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unsigned addr;
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#if CONFIG_PCI_IO_CFG_EXT == 0
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addr = (dev >> 4) | where;
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#else
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addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16); //seg == 0
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#endif
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inb(0xCFC + (addr & 3));
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}
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#if CONFIG_MMCONF_SUPPORT
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static u8 pci_mmio_rawread_config8(device_t_raw dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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return read8x(addr);
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}
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#endif
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static u8 pci_rawread_config8(device_t_raw dev, unsigned where)
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{
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#if CONFIG_MMCONF_SUPPORT
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return pci_mmio_rawread_config8(dev, where);
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#else
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return pci_io_rawread_config8(dev, where);
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#endif
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}
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static u16 pci_io_rawread_config16(device_t_raw dev, unsigned where)
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{
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unsigned addr;
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#if CONFIG_PCI_IO_CFG_EXT == 0
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addr = (dev >> 4) | where;
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#else
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addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
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#endif
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inw(0xCFC + (addr & 2));
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}
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#if CONFIG_MMCONF_SUPPORT
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static u16 pci_mmio_rawread_config16(device_t_raw dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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return read16x(addr);
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}
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#endif
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static u16 pci_rawread_config16(device_t_raw dev, unsigned where)
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{
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#if CONFIG_MMCONF_SUPPORT
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return pci_mmio_rawread_config16(dev, where);
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#else
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return pci_io_rawread_config16(dev, where);
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#endif
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}
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static u32 pci_io_rawread_config32(device_t_raw dev, unsigned where)
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{
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unsigned addr;
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#if CONFIG_PCI_IO_CFG_EXT == 0
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addr = (dev >> 4) | where;
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#else
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addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
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#endif
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outl(0x80000000 | (addr & ~3), 0xCF8);
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return inl(0xCFC);
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}
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#if CONFIG_MMCONF_SUPPORT
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static u32 pci_mmio_rawread_config32(device_t_raw dev, unsigned where)
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{
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unsigned addr;
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addr = dev | where;
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return read32x(addr);
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}
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#endif
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static u32 pci_rawread_config32(device_t_raw dev, unsigned where)
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{
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#if CONFIG_MMCONF_SUPPORT
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return pci_mmio_rawread_config32(dev, where);
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#else
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return pci_io_rawread_config32(dev, where);
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#endif
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}
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static void pci_io_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
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{
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unsigned addr;
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#if CONFIG_PCI_IO_CFG_EXT == 0
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addr = (dev >> 4) | where;
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#else
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addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
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#endif
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outb(value, 0xCFC + (addr & 3));
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}
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#if CONFIG_MMCONF_SUPPORT
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static void pci_mmio_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
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{
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unsigned addr;
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addr = dev | where;
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write8x(addr, value);
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}
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#endif
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static void pci_rawwrite_config8(device_t_raw dev, unsigned where, u8 value)
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{
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#if CONFIG_MMCONF_SUPPORT
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pci_mmio_rawwrite_config8(dev, where, value);
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#else
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pci_io_rawwrite_config8(dev, where, value);
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#endif
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}
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static void pci_io_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
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{
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unsigned addr;
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#if CONFIG_PCI_IO_CFG_EXT == 0
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addr = (dev >> 4) | where;
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#else
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addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
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#endif
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outw(value, 0xCFC + (addr & 2));
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}
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#if CONFIG_MMCONF_SUPPORT
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static void pci_mmio_rawwrite_config16(device_t_raw dev, unsigned where,
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u16 value)
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{
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unsigned addr;
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addr = dev | where;
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write16x(addr, value);
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}
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#endif
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static void pci_rawwrite_config16(device_t_raw dev, unsigned where, u16 value)
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{
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#if CONFIG_MMCONF_SUPPORT
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pci_mmio_rawwrite_config16(dev, where, value);
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#else
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pci_io_rawwrite_config16(dev, where, value);
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#endif
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}
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static void pci_io_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
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{
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unsigned addr;
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#if CONFIG_PCI_IO_CFG_EXT == 0
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addr = (dev >> 4) | where;
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#else
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addr = (dev >> 4) | (where & 0xff) | ((where & 0xf00) << 16);
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#endif
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outl(0x80000000 | (addr & ~3), 0xCF8);
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outl(value, 0xCFC);
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}
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#if CONFIG_MMCONF_SUPPORT
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static void pci_mmio_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
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{
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unsigned addr;
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addr = dev | where;
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write32x(addr, value);
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}
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#endif
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static void pci_rawwrite_config32(device_t_raw dev, unsigned where, u32 value)
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{
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#if CONFIG_MMCONF_SUPPORT
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pci_mmio_rawwrite_config32(dev, where, value);
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#else
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pci_io_rawwrite_config32(dev, where, value);
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#endif
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}
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static void pci_rawmodify_config8(device_t_raw dev, unsigned where, u8 orval, u8 mask)
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{
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u8 data = pci_rawread_config8(dev, where);
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u8 data = pci_read_config8(dev, where);
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data &= (~mask);
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data |= orval;
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pci_rawwrite_config8(dev, where, data);
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pci_write_config8(dev, where, data);
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}
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static void pci_rawmodify_config16(device_t_raw dev, unsigned where, u16 orval, u16 mask)
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static void pci_modify_config16(device_t dev, unsigned where, u16 orval, u16 mask)
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{
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u16 data = pci_rawread_config16(dev, where);
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u16 data = pci_read_config16(dev, where);
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data &= (~mask);
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data |= orval;
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pci_rawwrite_config16(dev, where, data);
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pci_write_config16(dev, where, data);
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}
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static void pci_rawmodify_config32(device_t_raw dev, unsigned where, u32 orval, u32 mask)
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static void pci_modify_config32(device_t dev, unsigned where, u32 orval, u32 mask)
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{
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u32 data = pci_rawread_config32(dev, where);
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u32 data = pci_read_config32(dev, where);
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data &= (~mask);
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data |= orval;
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pci_rawwrite_config32(dev, where, data);
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pci_write_config32(dev, where, data);
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}
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static void io_rawmodify_config8(u16 where, u8 orval, u8 mask)
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static void io_modify_config8(u16 where, u8 orval, u8 mask)
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{
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u8 data = inb(where);
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data &= (~mask);
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@ -262,7 +71,7 @@ static void via_pci_inittable(u8 chipversion,
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const struct VIA_PCI_REG_INIT_TABLE *initdata)
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{
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u8 i = 0;
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device_t_raw devbxdxfx;
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device_t devbxdxfx;
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for (i = 0;; i++) {
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if ((initdata[i].Mask == 0) && (initdata[i].Value == 0)
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&& (initdata[i].Bus == 0)
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@ -275,9 +84,9 @@ static void via_pci_inittable(u8 chipversion,
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if ((chipversion >= initdata[i].ChipRevisionStart)
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&& (chipversion <= initdata[i].ChipRevisionEnd)) {
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devbxdxfx =
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PCI_RAWDEV(initdata[i].Bus, initdata[i].Device,
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PCI_DEV(initdata[i].Bus, initdata[i].Device,
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initdata[i].Function);
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pci_rawmodify_config8(devbxdxfx,
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pci_modify_config8(devbxdxfx,
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initdata[i].Register,
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initdata[i].Value,
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initdata[i].Mask);
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@ -173,10 +173,10 @@ void SetUMARam(void)
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pci_write_config32(vga_dev, 0x14, Tmp);
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//enable direct cpu frame buffer access
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i = pci_rawread_config8(PCI_RAWDEV(0, 0, 3), 0xa1);
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i = pci_read_config8(PCI_DEV(0, 0, 3), 0xa1);
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i = (i & 0xf0) | (VIACONFIG_VGA_PCI_10 >> 28);
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pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa1, i);
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pci_rawwrite_config8(PCI_RAWDEV(0, 0, 3), 0xa0, 0x01);
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pci_write_config8(PCI_DEV(0, 0, 3), 0xa1, i);
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pci_write_config8(PCI_DEV(0, 0, 3), 0xa0, 0x01);
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//enable GFx memory space access control for S.L and mmio
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ByteVal = pci_read_config8(d0f0_dev, 0xD4);
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