GNUBoot/coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity

mb/google/brya: Add memory config for nissa

Browse source 
Fill in the memory config based on the the schematic and doc #573387.

BUG=b:197479026
TEST=abuild -a -x -c max -p none -t google/brya -b nivviks
     abuild -a -x -c max -p none -t google/brya -b nereid

Change-Id: I6958c7b74851879dbea41d181ef8f1282bf0101d
Signed-off-by: Reka Norman <rekanorman@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Reka Norman 2022-01-27 10:21:08 +11:00 committed by Felix Held
parent 8fb462fcc8
commit 9ec5f444d0
1 changed files with 90 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

94
src/mainboard/google/brya/variants/baseboard/nissa/memory.c
View file

@ -3,20 +3,106 @@
#include <baseboard/gpio.h>
#include <baseboard/variants.h>
#include <gpio.h>
#include <soc/romstage.h>
static const struct mb_cfg baseboard_memcfg = {
.type = MEM_TYPE_LP5X,
.rcomp = {
/* Baseboard uses only 100ohm Rcomp resistors */
.resistor = 100,
/* Baseboard Rcomp target values */
.targets = { 40, 36, 35, 35, 35 },
},
/* DQ byte map */
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
},
.ddr1 = {
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
},
.ddr2 = {
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
},
.ddr3 = {
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
},
.ddr4 = {
.dq0 = { 12, 9, 10, 11, 14, 13, 8, 15 },
.dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 },
},
.ddr5 = {
.dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 },
.dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 },
},
.ddr6 = {
.dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 },
.dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 },
},
.ddr7 = {
.dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 },
.dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 },
},
},
/* DQS CPU<>DRAM map */
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 1, .dqs1 = 0 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
},
.lp5x_config = {
.ccc_config = 0xff,
},
.ect = 1, /* Early Command Training */
.UserBd = BOARD_TYPE_MOBILE,
};
const struct mb_cfg *__weak variant_memory_params(void)
{
/* TODO */
return NULL;
return &baseboard_memcfg;
}
int __weak variant_memory_sku(void)
{
/*
* Memory configuration board straps
* GPIO_MEM_CONFIG_0 GPP_E1
* GPIO_MEM_CONFIG_1 GPP_E2
* GPIO_MEM_CONFIG_2 GPP_E3
*/
gpio_t spd_gpios[] = {
GPP_E1,
GPP_E2,
GPP_E3,
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
}
bool __weak variant_is_half_populated(void)
{
/* TODO */
/* ADL-N only has a single memory channel. */
return false;
}
void __weak variant_get_spd_info(struct mem_spd *spd_info)
{
/* TODO */
spd_info->topo = MEM_TOPO_MEMORY_DOWN;
spd_info->cbfs_index = variant_memory_sku();
}