From 9ec7227c9b43df97e3422877b2539db21d47741b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 17 Oct 2021 08:34:31 +0300 Subject: [PATCH] cpu/x86/lapic: Move LAPIC configuration to MP init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Implementation for setup_lapic() did two things -- call enable_lapic() and virtual_wire_mode_init(). In PARALLEL_MP case enable_lapic() was redundant as it was already executed prior to initialize_cpu() call. For the !PARALLEL_MP case enable_lapic() is added to AP CPUs. Change-Id: I5caf94315776a499e9cf8f007251b61f51292dc5 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/58387 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/cpu/amd/agesa/family14/model_14_init.c | 4 ---- src/cpu/amd/agesa/family15tn/model_15_init.c | 4 ---- src/cpu/amd/agesa/family16kb/model_16_init.c | 4 ---- src/cpu/amd/pi/00730F01/model_16_init.c | 4 ---- src/cpu/intel/common/common_init.c | 1 - src/cpu/intel/haswell/haswell_init.c | 3 --- src/cpu/intel/model_1067x/model_1067x_init.c | 4 ---- src/cpu/intel/model_106cx/model_106cx_init.c | 4 ---- src/cpu/intel/model_2065x/model_2065x_init.c | 2 -- src/cpu/intel/model_206ax/model_206ax_init.c | 3 --- src/cpu/intel/model_65x/model_65x_init.c | 4 ---- src/cpu/intel/model_67x/model_67x_init.c | 4 ---- src/cpu/intel/model_68x/model_68x_init.c | 4 ---- src/cpu/intel/model_6bx/model_6bx_init.c | 4 ---- src/cpu/intel/model_6ex/model_6ex_init.c | 4 ---- src/cpu/intel/model_6fx/model_6fx_init.c | 4 ---- src/cpu/intel/model_6xx/model_6xx_init.c | 4 ---- src/cpu/intel/model_f2x/model_f2x_init.c | 4 ---- src/cpu/intel/model_f3x/model_f3x_init.c | 4 ---- src/cpu/intel/model_f4x/model_f4x_init.c | 4 ---- src/cpu/qemu-x86/qemu.c | 2 -- src/cpu/x86/lapic/lapic.c | 22 +------------------- src/cpu/x86/lapic/lapic_cpu_init.c | 9 +++++++- src/cpu/x86/mp_init.c | 2 ++ src/include/cpu/x86/lapic.h | 2 +- src/soc/amd/cezanne/cpu.c | 2 -- src/soc/amd/picasso/cpu.c | 2 -- src/soc/amd/sabrina/cpu.c | 2 -- src/soc/amd/stoneyridge/cpu.c | 2 -- src/soc/intel/alderlake/cpu.c | 3 --- src/soc/intel/apollolake/cpu.c | 3 --- src/soc/intel/baytrail/cpu.c | 3 --- src/soc/intel/braswell/cpu.c | 3 --- src/soc/intel/cannonlake/cpu.c | 3 --- src/soc/intel/denverton_ns/cpu.c | 3 --- src/soc/intel/elkhartlake/cpu.c | 3 --- src/soc/intel/icelake/cpu.c | 3 --- src/soc/intel/jasperlake/cpu.c | 3 --- src/soc/intel/skylake/cpu.c | 3 --- src/soc/intel/tigerlake/cpu.c | 3 --- src/soc/intel/xeon_sp/cpx/chip.c | 2 -- src/soc/intel/xeon_sp/cpx/cpu.c | 2 -- 42 files changed, 12 insertions(+), 143 deletions(-) diff --git a/src/cpu/amd/agesa/family14/model_14_init.c b/src/cpu/amd/agesa/family14/model_14_init.c index 4cf0f45b82..8b67a95b9d 100644 --- a/src/cpu/amd/agesa/family14/model_14_init.c +++ b/src/cpu/amd/agesa/family14/model_14_init.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -57,9 +56,6 @@ static void model_14_init(struct device *dev) /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/agesa/family15tn/model_15_init.c b/src/cpu/amd/agesa/family15tn/model_15_init.c index d13fb9b135..77f9e9a8c6 100644 --- a/src/cpu/amd/agesa/family15tn/model_15_init.c +++ b/src/cpu/amd/agesa/family15tn/model_15_init.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -59,9 +58,6 @@ static void model_15_init(struct device *dev) /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/agesa/family16kb/model_16_init.c b/src/cpu/amd/agesa/family16kb/model_16_init.c index 2915565078..2ced7b9851 100644 --- a/src/cpu/amd/agesa/family16kb/model_16_init.c +++ b/src/cpu/amd/agesa/family16kb/model_16_init.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -57,9 +56,6 @@ static void model_16_init(struct device *dev) /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - #if CONFIG(LOGICAL_CPUS) siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/amd/pi/00730F01/model_16_init.c b/src/cpu/amd/pi/00730F01/model_16_init.c index f84b03ab3b..c743ffe3c5 100644 --- a/src/cpu/amd/pi/00730F01/model_16_init.c +++ b/src/cpu/amd/pi/00730F01/model_16_init.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -26,9 +25,6 @@ static void model_16_init(struct device *dev) /* zero the machine check error status registers */ mca_clear_status(); - /* Enable the local CPU APICs */ - setup_lapic(); - if (CONFIG(LOGICAL_CPUS)) { siblings = cpuid_ecx(0x80000008) & 0xff; diff --git a/src/cpu/intel/common/common_init.c b/src/cpu/intel/common/common_init.c index 0f40e4b1dd..24e3eeb60b 100644 --- a/src/cpu/intel/common/common_init.c +++ b/src/cpu/intel/common/common_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include "common.h" diff --git a/src/cpu/intel/haswell/haswell_init.c b/src/cpu/intel/haswell/haswell_init.c index d4f3587766..90ac5f4fad 100644 --- a/src/cpu/intel/haswell/haswell_init.c +++ b/src/cpu/intel/haswell/haswell_init.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -541,9 +540,7 @@ static void cpu_core_init(struct device *cpu) /* Clear out pending MCEs */ configure_mca(); - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_1067x/model_1067x_init.c b/src/cpu/intel/model_1067x/model_1067x_init.c index 33187d754e..02e6032265 100644 --- a/src/cpu/intel/model_1067x/model_1067x_init.c +++ b/src/cpu/intel/model_1067x/model_1067x_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -256,9 +255,6 @@ static void model_1067x_init(struct device *cpu) fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(quad); diff --git a/src/cpu/intel/model_106cx/model_106cx_init.c b/src/cpu/intel/model_106cx/model_106cx_init.c index 278d8dea81..4cf16d8831 100644 --- a/src/cpu/intel/model_106cx/model_106cx_init.c +++ b/src/cpu/intel/model_106cx/model_106cx_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -67,9 +66,6 @@ static void model_106cx_init(struct device *cpu) fill_processor_name(processor_name); printk(BIOS_INFO, "CPU: %s.\n", processor_name); - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_2065x/model_2065x_init.c b/src/cpu/intel/model_2065x/model_2065x_init.c index e77f9aaa75..35b153eb4b 100644 --- a/src/cpu/intel/model_2065x/model_2065x_init.c +++ b/src/cpu/intel/model_2065x/model_2065x_init.c @@ -91,9 +91,7 @@ static void model_2065x_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_206ax/model_206ax_init.c b/src/cpu/intel/model_206ax/model_206ax_init.c index 9de6b38198..52d11d72fe 100644 --- a/src/cpu/intel/model_206ax/model_206ax_init.c +++ b/src/cpu/intel/model_206ax/model_206ax_init.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include @@ -338,9 +337,7 @@ static void model_206ax_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ enable_lapic_tpr(); - setup_lapic(); /* Set virtualization based on Kconfig option */ set_vmx_and_lock(); diff --git a/src/cpu/intel/model_65x/model_65x_init.c b/src/cpu/intel/model_65x/model_65x_init.c index 9a17f7093f..15246b6396 100644 --- a/src/cpu/intel/model_65x/model_65x_init.c +++ b/src/cpu/intel/model_65x/model_65x_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -19,9 +18,6 @@ static void model_65x_init(struct device *dev) enable_cache(); x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_67x/model_67x_init.c b/src/cpu/intel/model_67x/model_67x_init.c index 6a2689ddb1..d524705031 100644 --- a/src/cpu/intel/model_67x/model_67x_init.c +++ b/src/cpu/intel/model_67x/model_67x_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -22,9 +21,6 @@ static void model_67x_init(struct device *cpu) /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_68x/model_68x_init.c b/src/cpu/intel/model_68x/model_68x_init.c index 2344cb7e9f..0b5d4541b9 100644 --- a/src/cpu/intel/model_68x/model_68x_init.c +++ b/src/cpu/intel/model_68x/model_68x_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -26,9 +25,6 @@ static void model_68x_init(struct device *cpu) /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6bx/model_6bx_init.c b/src/cpu/intel/model_6bx/model_6bx_init.c index f27a63ac50..0e54f934e6 100644 --- a/src/cpu/intel/model_6bx/model_6bx_init.c +++ b/src/cpu/intel/model_6bx/model_6bx_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -26,9 +25,6 @@ static void model_6bx_init(struct device *cpu) /* Setup MTRRs */ x86_setup_mtrrs(); x86_mtrr_check(); - - /* Enable the local CPU APICs */ - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_6ex/model_6ex_init.c b/src/cpu/intel/model_6ex/model_6ex_init.c index 34646ad5e9..bfa4a3e5f1 100644 --- a/src/cpu/intel/model_6ex/model_6ex_init.c +++ b/src/cpu/intel/model_6ex/model_6ex_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -106,9 +105,6 @@ static void model_6ex_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6fx/model_6fx_init.c b/src/cpu/intel/model_6fx/model_6fx_init.c index 72ece23935..a481a674f6 100644 --- a/src/cpu/intel/model_6fx/model_6fx_init.c +++ b/src/cpu/intel/model_6fx/model_6fx_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include @@ -120,9 +119,6 @@ static void model_6fx_init(struct device *cpu) /* Setup Page Attribute Tables (PAT) */ // TODO set up PAT - /* Enable the local CPU APICs */ - setup_lapic(); - /* Configure C States */ configure_c_states(); diff --git a/src/cpu/intel/model_6xx/model_6xx_init.c b/src/cpu/intel/model_6xx/model_6xx_init.c index 48a045ecc8..f9afc6cbad 100644 --- a/src/cpu/intel/model_6xx/model_6xx_init.c +++ b/src/cpu/intel/model_6xx/model_6xx_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include @@ -16,9 +15,6 @@ static void model_6xx_init(struct device *dev) /* Update the microcode */ intel_update_microcode_from_cbfs(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/intel/model_f2x/model_f2x_init.c b/src/cpu/intel/model_f2x/model_f2x_init.c index 9f365c6ebc..294d579f8e 100644 --- a/src/cpu/intel/model_f2x/model_f2x_init.c +++ b/src/cpu/intel/model_f2x/model_f2x_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -23,9 +22,6 @@ static void model_f2x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ intel_sibling_init(cpu); }; diff --git a/src/cpu/intel/model_f3x/model_f3x_init.c b/src/cpu/intel/model_f3x/model_f3x_init.c index ba3a4d60da..fdc5a1ef1d 100644 --- a/src/cpu/intel/model_f3x/model_f3x_init.c +++ b/src/cpu/intel/model_f3x/model_f3x_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -23,9 +22,6 @@ static void model_f3x_init(struct device *cpu) intel_update_microcode_from_cbfs(); } - /* Enable the local CPU APICs */ - setup_lapic(); - /* Start up my CPU siblings */ if (!CONFIG(PARALLEL_MP)) intel_sibling_init(cpu); diff --git a/src/cpu/intel/model_f4x/model_f4x_init.c b/src/cpu/intel/model_f4x/model_f4x_init.c index ee6761ed13..b495dee585 100644 --- a/src/cpu/intel/model_f4x/model_f4x_init.c +++ b/src/cpu/intel/model_f4x/model_f4x_init.c @@ -2,16 +2,12 @@ #include #include -#include #include static void model_f4x_init(struct device *cpu) { /* Turn on caching if we haven't already */ enable_cache(); - - /* Enable the local CPU APICs */ - setup_lapic(); }; static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/qemu-x86/qemu.c b/src/cpu/qemu-x86/qemu.c index 9f01007e2a..f0cdb58604 100644 --- a/src/cpu/qemu-x86/qemu.c +++ b/src/cpu/qemu-x86/qemu.c @@ -2,11 +2,9 @@ #include #include -#include static void qemu_cpu_init(struct device *dev) { - setup_lapic(); } static struct device_operations cpu_dev_ops = { diff --git a/src/cpu/x86/lapic/lapic.c b/src/cpu/x86/lapic/lapic.c index 9003534485..76f2d89db9 100644 --- a/src/cpu/x86/lapic/lapic.c +++ b/src/cpu/x86/lapic/lapic.c @@ -65,13 +65,7 @@ uintptr_t cpu_get_lapic_addr(void) return LAPIC_DEFAULT_BASE; } -/* See if I need to initialize the local APIC */ -static int need_lapic_init(void) -{ - return CONFIG(SMP) || CONFIG(IOAPIC); -} - -static void lapic_virtual_wire_mode_init(void) +void setup_lapic_interrupts(void) { /* * Set Task Priority to 'accept all'. @@ -94,17 +88,3 @@ static void lapic_virtual_wire_mode_init(void) lapic_update32(LAPIC_LVT1, ~mask, LAPIC_DELIVERY_MODE_NMI); } - -void setup_lapic(void) -{ - /* Enable the local APIC */ - if (need_lapic_init()) - enable_lapic(); - else if (!CONFIG(UDELAY_LAPIC)) - disable_lapic(); - - /* This programming is for PIC mode i8259 interrupts to be delivered to CPU - while LAPIC is enabled. */ - if (need_lapic_init()) - lapic_virtual_wire_mode_init(); -} diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c index 7780be26ec..837d32f3b6 100644 --- a/src/cpu/x86/lapic/lapic_cpu_init.c +++ b/src/cpu/x86/lapic/lapic_cpu_init.c @@ -298,6 +298,11 @@ asmlinkage void secondary_cpu_init(unsigned int index) cr4_val |= (CR4_OSFXSR | CR4_OSXMMEXCPT); write_cr4(cr4_val); #endif + + /* Ensure the local APIC is enabled */ + enable_lapic(); + setup_lapic_interrupts(); + cpu_initialize(index); spin_unlock(&start_cpu_lock); @@ -376,8 +381,10 @@ void initialize_cpus(struct bus *cpu_bus) info = cpu_info(); /* Ensure the local APIC is enabled */ - if (is_smp_boot()) + if (is_smp_boot()) { enable_lapic(); + setup_lapic_interrupts(); + } /* Get the device path of the boot CPU */ cpu_path.type = DEVICE_PATH_APIC; diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index abe903c62e..fee5940b18 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -185,6 +185,7 @@ static void asmlinkage ap_init(void) /* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts(); info->cpu = cpus_dev[info->index]; @@ -543,6 +544,7 @@ static void init_bsp(struct bus *cpu_bus) /* Ensure the local APIC is enabled */ enable_lapic(); + setup_lapic_interrupts(); /* Set the device path of the boot CPU. */ cpu_path.type = DEVICE_PATH_APIC; diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h index e131d2ec46..7006dbce1c 100644 --- a/src/include/cpu/x86/lapic.h +++ b/src/include/cpu/x86/lapic.h @@ -177,6 +177,6 @@ void stop_this_cpu(void); void enable_lapic(void); void disable_lapic(void); -void setup_lapic(void); +void setup_lapic_interrupts(void); #endif /* CPU_X86_LAPIC_H */ diff --git a/src/soc/amd/cezanne/cpu.c b/src/soc/amd/cezanne/cpu.c index 440b5ba28b..adc99d0ba6 100644 --- a/src/soc/amd/cezanne/cpu.c +++ b/src/soc/amd/cezanne/cpu.c @@ -8,7 +8,6 @@ #include #include #include -#include #include #include #include @@ -62,7 +61,6 @@ void mp_init_cpus(struct bus *cpu_bus) static void zen_2_3_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr(); amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/picasso/cpu.c b/src/soc/amd/picasso/cpu.c index b80b0f7a2e..de6e9c035b 100644 --- a/src/soc/amd/picasso/cpu.c +++ b/src/soc/amd/picasso/cpu.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -66,7 +65,6 @@ void mp_init_cpus(struct bus *cpu_bus) static void model_17_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr(); amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/sabrina/cpu.c b/src/soc/amd/sabrina/cpu.c index 0aa487c2f7..c355a704df 100644 --- a/src/soc/amd/sabrina/cpu.c +++ b/src/soc/amd/sabrina/cpu.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include @@ -64,7 +63,6 @@ void mp_init_cpus(struct bus *cpu_bus) static void zen_2_3_init(struct device *dev) { check_mca(); - setup_lapic(); set_cstate_io_addr(); amd_update_microcode_from_cbfs(); diff --git a/src/soc/amd/stoneyridge/cpu.c b/src/soc/amd/stoneyridge/cpu.c index 6be76bfde8..3cd3a9580a 100644 --- a/src/soc/amd/stoneyridge/cpu.c +++ b/src/soc/amd/stoneyridge/cpu.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -65,7 +64,6 @@ void mp_init_cpus(struct bus *cpu_bus) static void model_15_init(struct device *dev) { check_mca(); - setup_lapic(); /* * Per AMD, sync an undocumented MSR with the PSP base address. diff --git a/src/soc/intel/alderlake/cpu.c b/src/soc/intel/alderlake/cpu.c index 3b3a7a281c..426f6216b6 100644 --- a/src/soc/intel/alderlake/cpu.c +++ b/src/soc/intel/alderlake/cpu.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include @@ -110,9 +109,7 @@ void soc_core_init(struct device *cpu) * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/apollolake/cpu.c b/src/soc/intel/apollolake/cpu.c index 74aeee98e4..e8920174a3 100644 --- a/src/soc/intel/apollolake/cpu.c +++ b/src/soc/intel/apollolake/cpu.c @@ -5,7 +5,6 @@ #include #include "chip.h" #include -#include #include #include #include @@ -154,8 +153,6 @@ static void pre_mp_init(void) x86_setup_mtrrs_with_detect(); x86_mtrr_check(); - /* Enable the local CPU apics */ - setup_lapic(); } #if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT) diff --git a/src/soc/intel/baytrail/cpu.c b/src/soc/intel/baytrail/cpu.c index eb24f7bf8c..1dbc3d7751 100644 --- a/src/soc/intel/baytrail/cpu.c +++ b/src/soc/intel/baytrail/cpu.c @@ -36,9 +36,6 @@ static void soc_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init BayTrail core.\n"); - /* Enable the local CPU apics */ - setup_lapic(); - /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within diff --git a/src/soc/intel/braswell/cpu.c b/src/soc/intel/braswell/cpu.c index 7c7a15d19c..b11007d4f5 100644 --- a/src/soc/intel/braswell/cpu.c +++ b/src/soc/intel/braswell/cpu.c @@ -36,9 +36,6 @@ static void soc_core_init(struct device *cpu) { printk(BIOS_DEBUG, "Init Braswell core.\n"); - /* Enable the local cpu apics */ - setup_lapic(); - /* * The turbo disable bit is actually scoped at building block level -- not package. * For non-BSP cores that are within a building block, enable turbo. The cores within diff --git a/src/soc/intel/cannonlake/cpu.c b/src/soc/intel/cannonlake/cpu.c index 10921a2e9e..b7ca2b4db3 100644 --- a/src/soc/intel/cannonlake/cpu.c +++ b/src/soc/intel/cannonlake/cpu.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include @@ -118,9 +117,7 @@ void soc_core_init(struct device *cpu) * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure c-state interrupt response time */ configure_c_states(cfg); diff --git a/src/soc/intel/denverton_ns/cpu.c b/src/soc/intel/denverton_ns/cpu.c index 3747a48e68..93657fec02 100644 --- a/src/soc/intel/denverton_ns/cpu.c +++ b/src/soc/intel/denverton_ns/cpu.c @@ -100,9 +100,6 @@ static void denverton_core_init(struct device *cpu) /* Enable Turbo */ enable_turbo(); - /* Enable the local CPU apics */ - setup_lapic(); - /* Enable speed step. Always ON.*/ msr = rdmsr(IA32_MISC_ENABLE); msr.lo |= SPEED_STEP_ENABLE_BIT; diff --git a/src/soc/intel/elkhartlake/cpu.c b/src/soc/intel/elkhartlake/cpu.c index 0cc3935808..3e0dae191a 100644 --- a/src/soc/intel/elkhartlake/cpu.c +++ b/src/soc/intel/elkhartlake/cpu.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -70,9 +69,7 @@ void soc_core_init(struct device *cpu) * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/icelake/cpu.c b/src/soc/intel/icelake/cpu.c index 37978ea614..f503fcd051 100644 --- a/src/soc/intel/icelake/cpu.c +++ b/src/soc/intel/icelake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -103,9 +102,7 @@ void soc_core_init(struct device *cpu) * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure c-state interrupt response time */ configure_c_states(); diff --git a/src/soc/intel/jasperlake/cpu.c b/src/soc/intel/jasperlake/cpu.c index af39c94547..01cd6acac7 100644 --- a/src/soc/intel/jasperlake/cpu.c +++ b/src/soc/intel/jasperlake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include @@ -70,9 +69,7 @@ void soc_core_init(struct device *cpu) * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 63a04662e3..3439836f24 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include @@ -118,9 +117,7 @@ void soc_core_init(struct device *cpu) * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure c-state interrupt response time */ configure_c_states(); diff --git a/src/soc/intel/tigerlake/cpu.c b/src/soc/intel/tigerlake/cpu.c index d225c504c8..ffccdccf44 100644 --- a/src/soc/intel/tigerlake/cpu.c +++ b/src/soc/intel/tigerlake/cpu.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include @@ -76,9 +75,7 @@ void soc_core_init(struct device *cpu) * every bank. */ mca_configure(); - /* Enable the local CPU apics */ enable_lapic_tpr(); - setup_lapic(); /* Configure Enhanced SpeedStep and Thermal Sensors */ configure_misc(); diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index a4da3443c0..41dde0d84b 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -181,7 +180,6 @@ static void chip_init(void *data) override_hpet_ioapic_bdf(); pch_enable_ioapic(); pch_lock_dmictl(); - setup_lapic(); p2sb_unhide(); } diff --git a/src/soc/intel/xeon_sp/cpx/cpu.c b/src/soc/intel/xeon_sp/cpx/cpu.c index 07c2db7bbf..0951ae3fea 100644 --- a/src/soc/intel/xeon_sp/cpx/cpu.c +++ b/src/soc/intel/xeon_sp/cpx/cpu.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include @@ -78,7 +77,6 @@ static void each_cpu_init(struct device *cpu) printk(BIOS_SPEW, "%s dev: %s, cpu: %d, apic_id: 0x%x\n", __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id); - setup_lapic(); /* * Set HWP base feature, EPP reg enumeration, lock thermal and msr