samus: Update SPD with correct geometry and timings
This memory is also x16 and needs slight tweak to tRFCmin in order to be functional. BUG=chrome-os-partner:31833 BRANCH=None TEST=build and boot on EVT unit with this config Original-Change-Id: I01163ee7e70f08ccad84a3da39f1aac96e4c4771 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/217190 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Commit-Queue: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 6c4bf71c8c8e1e46ce290441c2e21bc7b2839760) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I389936d85e61a0a939cd4485fcc0723d2a0aa4d6 Reviewed-on: http://review.coreboot.org/8972 Reviewed-by: Aaron Durbin <adurbin@google.com> Tested-by: build bot (Jenkins)
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# Hynix H9CNNNNCLTMLAR-NTM LPDDR3
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# banks 8, ranks 2, rows 15, columns 11, density 16384 Mb, x32
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91 20 F1 03 06 1A 05 0B 03 11 01 08 0A 00 50 01
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78 78 90 50 90 11 50 E0 10 04 3C 3C 01 90 00 00
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# Hynix H9CCNNNCLTMLAR LPDDR3
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# banks 8, ranks 2, rows 15, columns 11, density 8192 Mb, x16
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91 20 F1 03 05 1A 05 0A 03 11 01 08 0A 00 50 01
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78 78 90 50 90 11 50 E0 90 06 3C 3C 01 90 00 00
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00 80 00 00 00 00 00 A8 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 0F 01 02 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 80 AD 00 00 00 55 00 00 00 00 00
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48 39 43 43 4E 4E 4E 42 4C 54 4D 4C 41 52 2D 4E
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54 4D 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
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48 39 43 43 4E 4E 4E 43 4C 54 4D 4C 41 52 00 00
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00 00 00 00 80 AD 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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