sb/intel/i82801ix: Add common code to set up LPC IO decode ranges
This does the following: - Add gen[1-4]_dec options to the devicetree to set up generic LPC decode ranges in the southbridge code. - Move setting up some default decode ranges to a common place. If somehow a board needs to override this behavior it can happen in the mb_setup_superio() hook (that will be renamed when moving to C_ENVIRONMENT_BOOTBLOCK). Change-Id: I3d904b1125bc410c11aa73a89b1969284e88dac1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35991 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -75,6 +75,9 @@ chip northbridge/intel/gm45
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# Maybe we should set less for Mini PCIe.
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register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
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register "gen1_dec" = "0x007c1601"
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register "gen2_dec" = "0x000c15e1"
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register "gen3_dec" = "0x001c1681"
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device pci 19.0 on end # LAN
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device pci 1a.0 on # UHCI
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@ -14,16 +14,12 @@
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <southbridge/intel/i82801ix/i82801ix.h>
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#include <southbridge/intel/common/gpio.h>
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#include <northbridge/intel/gm45/gm45.h>
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#include <drivers/lenovo/hybrid_graphics/hybrid_graphics.h>
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#include "dock.h"
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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static void hybrid_graphics_init(sysinfo_t *sysinfo)
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{
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bool peg, igd;
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@ -36,20 +32,6 @@ static void hybrid_graphics_init(sysinfo_t *sysinfo)
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static int dock_err;
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void mb_setup_lpc(void)
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{
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/* Set up SuperIO LPC forwards */
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/* Configure serial IRQs.*/
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pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
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/* Map COMa on 0x3f8, COMb on 0x2f8. */
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pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
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pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
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pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
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pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
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pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
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}
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void mb_setup_superio(void)
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{
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/* Minimal setup to detect dock */
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@ -79,6 +79,9 @@ chip northbridge/intel/gm45
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# Maybe we should set less for Mini PCIe.
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register "pcie_power_limits" = "{ { 10, 0 }, { 10, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 }, { 0, 0 } }"
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register "pcie_hotplug_map" = "{ 0, 0, 0, 1, 0, 0, 0, 0 }"
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register "gen1_dec" = "0x007c1601"
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register "gen2_dec" = "0x000c15e1"
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register "gen3_dec" = "0x001c1681"
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device pci 19.0 on end # LAN
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device pci 1a.0 on # UHCI
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@ -14,25 +14,9 @@
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/i82801ix/i82801ix.h>
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#include <northbridge/intel/gm45/gm45.h>
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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void mb_setup_lpc(void)
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{
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/* Configure serial IRQs.*/
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pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
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/* Map COMa on 0x3f8, COMb on 0x2f8. */
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pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
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pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3f0f);
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pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x7c1601);
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pci_write_config32(LPC_DEV, D31F0_GEN2_DEC, 0xc15e1);
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pci_write_config32(LPC_DEV, D31F0_GEN3_DEC, 0x1c1681);
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}
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void get_mb_spd_addrmap(u8 *spd_addrmap)
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{
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spd_addrmap[0] = 0x50;
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@ -67,6 +67,8 @@ chip northbridge/intel/gm45
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# Maybe we should set less for Mini PCIe.
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register "pcie_power_limits" = "{ { 10, 0 }, { 0, 0 }, { 0, 0 }, { 0, 0 }, { 10, 0 }, { 0, 0 } }"
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register "gen1_dec" = "0x000c0601"
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device pci 19.0 off end # LAN
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device pci 1a.0 on # UHCI
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ioapic_irq 2 INTA 0x10
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@ -16,27 +16,11 @@
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#include <arch/io.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <southbridge/intel/common/gpio.h>
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#include <southbridge/intel/i82801ix/i82801ix.h>
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#include <northbridge/intel/gm45/gm45.h>
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#include <superio/smsc/lpc47n227/lpc47n227.h>
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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#define SERIAL_DEV PNP_DEV(0x2e, LPC47N227_SP1)
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void mb_setup_lpc(void)
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{
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/* Set up SuperIO LPC forwards */
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/* Configure serial IRQs.*/
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pci_write_config8(LPC_DEV, D31F0_SERIRQ_CNTL, 0xd0);
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/* Map COMa on 0x3f8, COMb on 0x2f8. */
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pci_write_config16(LPC_DEV, D31F0_LPC_IODEC, 0x0010);
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/* Enable COMa, COMb, Kbd, SuperIO at 0x2e, MCs at 0x4e and 0x62/66. */
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pci_write_config16(LPC_DEV, D31F0_LPC_EN, 0x3c03);
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}
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void mb_setup_superio(void)
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{
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/* Original settings:
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@ -71,9 +55,6 @@ void mb_setup_superio(void)
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/* Exit configuration state. */
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pnp_exit_conf_state(sio);
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/* Enable decoding of 0x600-0x60f through lpc. */
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pci_write_config32(LPC_DEV, D31F0_GEN1_DEC, 0x000c0601);
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/* Set GPIO output values: */
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outb(0x88, 0x600 + 0xb + 3); /* GP30 - GP37 */
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outb(0x10, 0x600 + 0xb + 4); /* GP40 - GP47 */
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@ -435,7 +435,6 @@ u32 decode_tseg_size(u8 esmramc);
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void init_iommu(void);
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/* romstage mainboard hookups */
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void mb_setup_lpc(void);
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void mb_setup_superio(void); /* optional */
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void get_mb_spd_addrmap(u8 spd_addrmap[4]);
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void mb_pre_raminit_setup(sysinfo_t *); /* optional */
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@ -62,7 +62,7 @@ void mainboard_romstage_entry(void)
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i82801ix_early_init();
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setup_pch_gpios(&mainboard_gpio_map);
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mb_setup_lpc();
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i82801ix_lpc_decode();
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mb_setup_superio();
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@ -88,6 +88,12 @@ struct southbridge_intel_i82801ix_config {
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} pcie_power_limits[6];
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uint8_t pcie_hotplug_map[8];
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/* Additional LPC IO decode ranges */
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uint32_t gen1_dec;
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uint32_t gen2_dec;
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uint32_t gen3_dec;
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uint32_t gen4_dec;
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};
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#endif /* SOUTHBRIDGE_INTEL_I82801IX_CHIP_H */
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@ -17,6 +17,7 @@
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#include <arch/io.h>
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#include <device/pci_ops.h>
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#include "i82801ix.h"
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#include "chip.h"
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void i82801ix_early_init(void)
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{
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@ -58,3 +59,34 @@ void i82801ix_early_init(void)
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/* TODO: Check power state bits in GEN_PMCON_2 (D31F0 0xa2)
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before they get cleared. */
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}
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void i82801ix_lpc_decode(void)
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{
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const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0);
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const struct device *dev = pcidev_on_root(0x1f, 0);
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const struct southbridge_intel_i82801ix_config *config = NULL;
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/* Configure serial IRQs.*/
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pci_write_config8(d31f0, D31F0_SERIRQ_CNTL, 0xd0);
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/*
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* Enable some common LPC IO ranges:
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* - 0x2e/0x2f, 0x4e/0x4f often SuperIO
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* - 0x60/0x64, 0x62/0x66 often KBC/EC
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* - 0x3f0-0x3f5/0x3f7 FDD
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* - 0x378-0x37f and 0x778-0x77f LPT
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* - 0x2f8-0x2ff COMB
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* - 0x3f8-0x3ff COMA
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*/
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pci_write_config16(d31f0, D31F0_LPC_IODEC, 0x0010);
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pci_write_config16(d31f0, D31F0_LPC_EN, 0x3f0f);
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/* Set up generic decode ranges */
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if (!dev || !dev->chip_info)
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return;
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config = dev->chip_info;
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pci_write_config32(d31f0, D31F0_GEN1_DEC, config->gen1_dec);
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pci_write_config32(d31f0, D31F0_GEN2_DEC, config->gen2_dec);
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pci_write_config32(d31f0, D31F0_GEN3_DEC, config->gen3_dec);
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pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec);
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}
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@ -210,6 +210,7 @@ void aseg_smm_lock(void);
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void enable_smbus(void);
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void i82801ix_early_init(void);
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void i82801ix_lpc_decode(void);
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void i82801ix_dmi_setup(void);
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void i82801ix_dmi_poll_vc1(void);
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