mb/intel/jasperlake_rvp: Correct Kconfig options

1.Select CHROMEOS_EC related Kconfig for variant board with
  external EC support.
2.Select proper CHROMEOS Kconfigs which are required for all
  variants.
3.Disable Intel EC region in case of external EC.

BUG=None
BRANCH=None
TEST=Compilation is successful for both Jasper Lake RVP variants.

Change-Id: I290b3748777e18476651101de71df9080dd3105c
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39584
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Maulik V Vaghela 2020-03-16 21:10:06 +05:30 committed by Patrick Georgi
parent aa56c11b19
commit 9ed5a36e98
2 changed files with 21 additions and 4 deletions

View File

@ -10,9 +10,7 @@ config BOARD_SPECIFIC_OPTIONS
select GENERIC_SPD_BIN
select HAVE_ACPI_RESUME
select HAVE_ACPI_TABLES
select INTEL_LPSS_UART_FOR_CONSOLE
select MAINBOARD_HAS_CHROMEOS
select MAINBOARD_USES_IFD_EC_REGION
select SOC_INTEL_JASPERLAKE
config MAINBOARD_DIR
@ -43,11 +41,24 @@ config DIMM_SPD_SIZE
int
default 512
config CHROMEOS
bool
default y
select GBB_FLAG_FORCE_DEV_SWITCH_ON
select GBB_FLAG_FORCE_DEV_BOOT_USB
select GBB_FLAG_FORCE_DEV_BOOT_LEGACY
select GBB_FLAG_FORCE_MANUAL_RECOVERY
select GBB_FLAG_DISABLE_PD_SOFTWARE_SYNC
select HAS_RECOVERY_MRC_CACHE
select MRC_CLEAR_NORMAL_CACHE_ON_RECOVERY_RETRAIN
config VBOOT
select VBOOT_LID_SWITCH
select VBOOT_MOCK_SECDATA
select VBOOT_MOCK_SECDATA if !MAINBOARD_HAS_TPM2
config UART_FOR_CONSOLE
int
default 2
default 2 if INTEL_LPSS_UART_FOR_CONSOLE
default 0
endif

View File

@ -1,5 +1,11 @@
config BOARD_INTEL_JASPERLAKE_RVP
bool "Jasperlake DDR4/LPDDR4 RVP"
select DRIVERS_UART_8250IO
select MAINBOARD_USES_IFD_EC_REGION
config BOARD_INTEL_JASPERLAKE_RVP_EXT_EC
bool "Jasperlake DDR4/LPDDR4 RVP with Chrome EC"
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_LPC
select EC_GOOGLE_CHROMEEC_SWITCHES
select INTEL_LPSS_UART_FOR_CONSOLE