nb/amd/pi/00730F01: Add initial native IVRS support
- Iteration over devices in add_ivrs_device_entries were simplified to decrease complexity. - Code was structured to satisfy checkpatch Change-Id: I1ae789f75363435accd14a1b556e1570f43f94c4 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/15164 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Timothy Pearson
Patrick Georgi
parent
03eb8a8515
commit
9ef07d8623
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@ -2,6 +2,8 @@
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* This file is part of the coreboot project.
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* This file is part of the coreboot project.
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*
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*
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2012 Advanced Micro Devices, Inc.
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* Copyright (C) 2016 Raptor Engineering, LLC
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* Copyright (C) 2018 3mdeb Embedded Systems Consulting
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*
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*
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* This program is free software; you can redistribute it and/or modify
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* it under the terms of the GNU General Public License as published by
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@ -437,6 +439,208 @@ static unsigned long acpi_fill_hest(acpi_hest_t *hest)
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return (unsigned long)current;
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return (unsigned long)current;
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}
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}
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static void add_ivhd_dev_entry(struct device *parent, struct device *dev,
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unsigned long *current, uint16_t *length,
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uint8_t type, uint8_t data)
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{
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uint8_t *p;
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p = (uint8_t *) *current;
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if (type == 0x2) {
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/* Entry type */
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p[0] = type;
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/* Device */
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p[1] = dev->path.pci.devfn;
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/* Bus */
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p[2] = dev->bus->secondary;
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/* Data */
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p[3] = data;
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/* [4:7] Padding */
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p[4] = 0x0;
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p[5] = 0x0;
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p[6] = 0x0;
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p[7] = 0x0;
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*length += 8;
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*current += 8;
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} else if (type == 0x42) {
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/* Entry type */
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p[0] = type;
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/* Device */
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p[1] = dev->path.pci.devfn;
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/* Bus */
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p[2] = dev->bus->secondary;
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/* Data */
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p[3] = 0x0;
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/* Reserved */
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p[4] = 0x0;
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/* Device */
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p[5] = parent->path.pci.devfn;
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/* Bus */
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p[6] = parent->bus->secondary;
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/* Reserved */
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p[7] = 0x0;
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*length += 8;
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*current += 8;
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}
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}
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static void add_ivrs_device_entries(struct device *parent, struct device *dev,
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unsigned int depth, int linknum, int8_t *root_level,
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unsigned long *current, uint16_t *length)
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{
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struct device *sibling;
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struct bus *link;
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unsigned int header_type;
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unsigned int is_pcie;
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if (!root_level) {
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root_level = malloc(sizeof(int8_t));
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*root_level = -1;
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}
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if (dev->path.type == DEVICE_PATH_PCI) {
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if ((dev->bus->secondary == 0x0) &&
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(dev->path.pci.devfn == 0x0))
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*root_level = depth;
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if ((*root_level != -1) && (dev->enabled)) {
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if (depth == *root_level) {
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if (dev->path.pci.devfn == (0x14 << 3)) {
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/* SMBUS controller */
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add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x97);
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} else if (dev->path.pci.devfn != 0x2 &&
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dev->path.pci.devfn < (0x2 << 3)) {
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/* FCH control device */
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} else {
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/* Other devices */
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add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0);
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}
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} else {
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header_type = dev->hdr_type & 0x7f;
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is_pcie = pci_find_capability(dev, PCI_CAP_ID_PCIE);
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if (((header_type == PCI_HEADER_TYPE_NORMAL) ||
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(header_type == PCI_HEADER_TYPE_BRIDGE))
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&& is_pcie) {
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/* Device or Bridge is PCIe */
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add_ivhd_dev_entry(parent, dev, current, length, 0x2, 0x0);
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} else if ((header_type == PCI_HEADER_TYPE_NORMAL) &&
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!is_pcie) {
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add_ivhd_dev_entry(parent, dev, current, length, 0x42, 0x0);
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/* Device is legacy PCI or PCI-X */
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}
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}
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}
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}
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for (link = dev->link_list; link; link = link->next)
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for (sibling = link->children; sibling; sibling =
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sibling->sibling)
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add_ivrs_device_entries(dev, sibling, depth + 1, depth,
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root_level, current, length);
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free(root_level);
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}
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unsigned long acpi_fill_ivrs_ioapic(acpi_ivrs_t *ivrs, unsigned long current)
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{
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uint8_t *p;
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uint32_t apicid_sb800;
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uint32_t apicid_northbridge;
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apicid_sb800 = CONFIG_MAX_CPUS;
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apicid_northbridge = CONFIG_MAX_CPUS + 1;
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/* Describe NB IOAPIC */
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p = (uint8_t *)current;
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p[0] = 0x48; /* Entry type */
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p[1] = 0; /* Device */
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p[2] = 0; /* Bus */
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p[3] = 0x0; /* Data */
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p[4] = apicid_northbridge; /* IOAPIC ID */
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p[5] = 0x0; /* Device 0 Function 0 */
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p[6] = 0x0; /* Northbridge bus */
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p[7] = 0x1; /* Variety */
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current += 8;
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/* Describe SB IOAPIC */
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p = (uint8_t *)current;
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p[0] = 0x48; /* Entry type */
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p[1] = 0; /* Device */
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p[2] = 0; /* Bus */
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p[3] = 0xd7; /* Data */
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p[4] = apicid_sb800; /* IOAPIC ID */
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p[5] = 0x14 << 3; /* Device 0x14 Function 0 */
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p[6] = 0x0; /* Southbridge bus */
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p[7] = 0x1; /* Variety */
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current += 8;
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return current;
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}
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static unsigned long acpi_fill_ivrs(acpi_ivrs_t *ivrs, unsigned long current)
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{
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uint8_t *p;
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device_t nb_dev = dev_find_slot(0, PCI_DEVFN(0, 0));
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if (!nb_dev) {
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printk(BIOS_WARNING, "%s: G-series northbridge device not present!\n", __func__);
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printk(BIOS_WARNING, "%s: IVRS table not generated...\n", __func__);
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return (unsigned long)ivrs;
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}
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ivrs->iv_info = 0x0;
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/* Maximum supported virtual address size */
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ivrs->iv_info |= (0x40 << 15);
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/* Maximum supported physical address size */
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ivrs->iv_info |= (0x30 << 8);
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/* Guest virtual address width */
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ivrs->iv_info |= (0x2 << 5);
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ivrs->ivhd.type = 0x10;
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ivrs->ivhd.flags = 0x0e;
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/* Enable ATS support */
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ivrs->ivhd.flags |= 0x10;
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ivrs->ivhd.length = sizeof(struct acpi_ivrs_ivhd);
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/* BDF <bus>:00.2 */
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ivrs->ivhd.device_id = 0x2 | (nb_dev->bus->secondary << 8);
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/* Capability block 0x40 (type 0xf, "Secure device") */
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ivrs->ivhd.capability_offset = 0x40;
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ivrs->ivhd.iommu_base_low = 0xfeb00000;
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ivrs->ivhd.iommu_base_high = 0x0;
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ivrs->ivhd.pci_segment_group = 0x0;
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ivrs->ivhd.iommu_info = 0x0;
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ivrs->ivhd.iommu_info |= (0x13 << 8);
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ivrs->ivhd.iommu_feature_info = 0x0;
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/* Describe HPET */
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p = (uint8_t *)current;
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p[0] = 0x48; /* Entry type */
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p[1] = 0; /* Device */
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p[2] = 0; /* Bus */
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p[3] = 0xd7; /* Data */
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p[4] = 0x0; /* HPET number */
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p[5] = 0x14 << 3; /* HPET device */
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p[6] = nb_dev->bus->secondary; /* HPET bus */
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p[7] = 0x2; /* Variety */
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ivrs->ivhd.length += 8;
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current += 8;
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/* Describe PCI devices */
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add_ivrs_device_entries(NULL, all_devices, 0, -1, NULL, ¤t,
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&ivrs->ivhd.length);
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/* Describe IOAPICs */
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unsigned long prev_current = current;
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current = acpi_fill_ivrs_ioapic(ivrs, current);
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ivrs->ivhd.length += (current - prev_current);
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return current;
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}
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static void northbridge_fill_ssdt_generator(struct device *device)
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static void northbridge_fill_ssdt_generator(struct device *device)
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{
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{
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msr_t msr;
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msr_t msr;
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@ -466,7 +670,7 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
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acpi_slit_t *slit;
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acpi_slit_t *slit;
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acpi_header_t *ssdt;
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acpi_header_t *ssdt;
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acpi_header_t *alib;
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acpi_header_t *alib;
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acpi_header_t *ivrs;
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acpi_ivrs_t *ivrs;
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acpi_hest_t *hest;
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acpi_hest_t *hest;
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/* HEST */
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/* HEST */
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@ -476,17 +680,13 @@ static unsigned long agesa_write_acpi_tables(struct device *device,
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acpi_add_table(rsdp, (void *)current);
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acpi_add_table(rsdp, (void *)current);
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current += ((acpi_header_t *)current)->length;
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current += ((acpi_header_t *)current)->length;
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current = ALIGN(current, 8);
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/* IVRS */
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printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
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current = ALIGN(current, 8);
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ivrs = agesawrapper_getlateinitptr(PICK_IVRS);
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printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current);
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if (ivrs != NULL) {
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ivrs = (acpi_ivrs_t *) current;
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memcpy((void *)current, ivrs, ivrs->length);
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acpi_create_ivrs(ivrs, acpi_fill_ivrs);
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ivrs = (acpi_header_t *) current;
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current += ivrs->header.length;
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current += ivrs->length;
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acpi_add_table(rsdp, ivrs);
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acpi_add_table(rsdp, ivrs);
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} else {
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printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n");
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}
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/* SRAT */
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/* SRAT */
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current = ALIGN(current, 8);
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current = ALIGN(current, 8);
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