GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/kahlee: move SMI/SCI GPIO setup to ramstage 

SMIs and SCIs aren't used before ramstage or the OS, so there should be
no need to already set them up in romstage. Not using this GPIO
configuration functionality allows untangling the GPIO and smi_util code
and only linking smi_util in ramstage in follow-up patches. In romstage
the pins get initialized as inputs with pull-up, so that at least that
part still matches the configuration before this patch.

BUG=b:175386410

Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Felix Held 2020-12-12 22:28:54 +01:00
parent 815efe16cb
commit 9ef72ca7db
1 changed files with 15 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/mainboard/google/kahlee/variants/baseboard/gpio.c
View File

@ -15,8 +15,8 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_4 - EN_PP3300_WLAN */ /* GPIO_4 - EN_PP3300_WLAN */
PAD_GPO(GPIO_4, HIGH), PAD_GPO(GPIO_4, HIGH),
/* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI gets configured in ramstage */
PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW), PAD_GPI(GPIO_6, PULL_UP),
/* GPIO_9 - H1_PCH_INT_ODL */ /* GPIO_9 - H1_PCH_INT_ODL */
PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS), PAD_INT(GPIO_9, PULL_UP, EDGE_LOW, STATUS),
@ -24,11 +24,11 @@ static const struct soc_amd_gpio gpio_set_stage_reset[] = {
/* GPIO_15 - EC_IN_RW_OD */ /* GPIO_15 - EC_IN_RW_OD */
PAD_GPI(GPIO_15, PULL_UP), PAD_GPI(GPIO_15, PULL_UP),
/* GPIO_22 - EC_SCI_ODL, SCI */ /* GPIO_22 - EC_SCI_ODL, SCI gets configured in ramstage */
PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW), PAD_GPI(GPIO_22, PULL_UP),
/* GPIO_24 - EC_PCH_WAKE_L, SCI */ /* GPIO_24 - EC_PCH_WAKE_L, SCI gets configured in ramstage */
PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW), PAD_GPI(GPIO_24, PULL_UP),
/* GPIO_26 - APU_PCIE_RST_L */ /* GPIO_26 - APU_PCIE_RST_L */
PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE), PAD_NF(GPIO_26, PCIE_RST_L, PULL_NONE),
@ -90,6 +90,9 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */
PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW), PAD_SCI(GPIO_5, PULL_UP, EDGE_LOW),
/* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */
PAD_SMI(GPIO_6, PULL_UP, LEVEL_LOW),
/* GPIO_7 - APU_PWROK_OD (currently not used) */ /* GPIO_7 - APU_PWROK_OD (currently not used) */
PAD_GPI(GPIO_7, PULL_UP), PAD_GPI(GPIO_7, PULL_UP),
@ -129,6 +132,12 @@ static const struct soc_amd_gpio gpio_set_stage_ram[] = {
/* GPIO_21 - APU_PEN_INT_ODL, SCI */ /* GPIO_21 - APU_PEN_INT_ODL, SCI */
PAD_SCI(GPIO_21, PULL_UP, EDGE_LOW), PAD_SCI(GPIO_21, PULL_UP, EDGE_LOW),
/* GPIO_22 - EC_SCI_ODL, SCI */
PAD_SCI(GPIO_22, PULL_UP, EDGE_LOW),
/* GPIO_24 - EC_PCH_WAKE_L, SCI */
PAD_SCI(GPIO_24, PULL_UP, EDGE_LOW),
/* GPIO_25 - SD_CD */ /* GPIO_25 - SD_CD */
PAD_NF(GPIO_25, SD0_CD, PULL_UP), PAD_NF(GPIO_25, SD0_CD, PULL_UP),