arch/x86: Only use .bss from car.ld when running XIP
Some platform run early stages like romstage and verstage from CAR instead of XIP. This allows to link them like other arch inside the _program region. This make in place LZ4 decompression possible as it needs a bit of extra place to extract the code which is now provided by the .bss. Tested on up/squared (Intel APL). Change-Id: I6cf51f943dde5f642d75ba4c5d3be520dc56370a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Nico Huber <nico.h@gmx.de>
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@ -34,6 +34,7 @@ _start:
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mov $_STACK_TOP, %esp
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/* clear .bss section as it is not shared */
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#if ENV_SEPARATE_BSS
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cld
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xor %eax, %eax
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movl $(_ebss), %ecx
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@ -41,6 +42,7 @@ _start:
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sub %edi, %ecx
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shrl $2, %ecx
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rep stosl
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#endif
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#if ((ENV_SEPARATE_VERSTAGE && CONFIG(VERSTAGE_DEBUG_SPINLOOP)) \
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|| (ENV_ROMSTAGE && CONFIG(ROMSTAGE_DEBUG_SPINLOOP)))
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@ -59,6 +59,7 @@
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* cbmem console. This is useful for clearing this area on a per-stage
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* basis when more than one stage uses cache-as-ram. */
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#if ENV_SEPARATE_BSS
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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_bss = .;
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/* Allow global uninitialized variables for stages without CAR teardown. */
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@ -69,6 +70,7 @@
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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_ebss = .;
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RECORD_SIZE(bss)
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#endif
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#if ENV_ROMSTAGE && CONFIG(ASAN_IN_ROMSTAGE)
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_shadow_size = (_ebss - _car_region_start) >> 3;
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@ -275,6 +275,9 @@
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#define ENV_CACHE_AS_RAM 0
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#endif
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/* Indicates if the stage uses the _bss region defined in arch/x86/car.ld */
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#define ENV_SEPARATE_BSS (ENV_CACHE_AS_RAM && (ENV_BOOTBLOCK || !CONFIG(NO_XIP_EARLY_STAGES)))
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/* Currently rmodules, ramstage and smm have heap. */
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#define ENV_HAS_HEAP_SECTION (ENV_RMODULE || ENV_RAMSTAGE || ENV_SMM)
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@ -116,7 +116,7 @@
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}
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#endif
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#if !ENV_CACHE_AS_RAM
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#if !ENV_SEPARATE_BSS
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.bss . : {
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. = ALIGN(ARCH_POINTER_ALIGN_SIZE);
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_bss = .;
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