mb/google/corsola: Enable Chrome EC

Initialize SPI bus 1 for Chrome EC control.

TEST=build pass
BUG=b:202871018

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Rex-BC Chen 2021-11-18 15:20:42 +08:00 committed by Hung-Te Lin
parent eb102ccbd6
commit 9f01bbf410
4 changed files with 17 additions and 6 deletions

View File

@ -6,16 +6,24 @@ config BOARD_GOOGLE_CORSOLA_COMMON
if BOARD_GOOGLE_CORSOLA_COMMON
config VBOOT
select EC_GOOGLE_CHROMEEC_SWITCHES
select VBOOT_VBNV_FLASH
config BOARD_SPECIFIC_OPTIONS
def_bool y
select SOC_MEDIATEK_MT8186
select BOARD_ROMSIZE_KB_8192
select MAINBOARD_HAS_CHROMEOS
select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS
select COMMON_CBFS_SPI_WRAPPER
select SPI_FLASH
select SPI_FLASH_INCLUDE_ALL_DRIVERS
select COMMONLIB_STORAGE
select COMMONLIB_STORAGE_MMC
select EC_GOOGLE_CHROMEEC
select EC_GOOGLE_CHROMEEC_BOARDID
select EC_GOOGLE_CHROMEEC_SPI
config MAINBOARD_DIR
string
@ -34,4 +42,8 @@ config BOOT_DEVICE_SPI_FLASH_BUS
config SDCARD_INIT
bool
default n
config EC_GOOGLE_CHROMEEC_SPI_BUS
hex
default 0x1
endif

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@ -8,6 +8,7 @@
void bootblock_mainboard_init(void)
{
mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
mtk_snfc_init(SPI_NOR_GPIO_SET0);
setup_chromeos_gpios();
}

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@ -26,9 +26,3 @@ void fill_lb_gpios(struct lb_gpios *gpios)
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_recovery_mode_switch(void)
{
/* TODO: use Chrome EC switches when EC support is added */
return 0;
}

View File

@ -1,7 +1,11 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <gpio.h>
#include <reset.h>
#include "gpio.h"
void do_board_reset(void)
{
gpio_output(GPIO_RESET, 1);
}