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soc/intel/cannonlake: Lock PAM registers in finalize 

Use the support from the previous patch to have coreboot lock the PAM
registers instead of the FSP when the lockdown configuration is set to
coreboot.

Change-Id: I6ae22f9df4834508dfa304050fad44d45df45334
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Tim Wawrzynczak 2021-08-26 09:17:53 -06:00 committed by Felix Held
parent 9ed1751676
commit 9f0266c599
2 changed files with 10 additions and 0 deletions
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9
src/soc/intel/cannonlake/finalize.c
View File

@ -10,8 +10,10 @@
#include <intelblocks/lpc_lib.h>
#include <intelblocks/pcr.h>
#include <intelblocks/pmclib.h>
#include <intelblocks/systemagent.h>
#include <intelblocks/tco.h>
#include <intelblocks/thermal.h>
#include <intelpch/lockdown.h>
#include <soc/p2sb.h>
#include <soc/pci_devs.h>
#include <soc/pcr_ids.h>
@ -80,12 +82,19 @@ static void pch_finalize(void)
}
static void sa_finalize(void)
{
if (get_lockdown_config() == CHIPSET_LOCKDOWN_COREBOOT)
sa_lock_pam();
}
static void soc_finalize(void *unused)
{
printk(BIOS_DEBUG, "Finalizing chipset.\n");
pch_finalize();
apm_control(APM_CNT_FINALIZE);
sa_finalize();
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);

1
src/soc/intel/cannonlake/fsp_params.c
View File

@ -653,6 +653,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
tconfig->PchLockDownBiosInterface = lockdown_by_fsp;
params->PchLockDownBiosLock = lockdown_by_fsp;
params->PchLockDownRtcMemoryLock = lockdown_by_fsp;
tconfig->SkipPamLock = !lockdown_by_fsp;
#if CONFIG(SOC_INTEL_COMETLAKE)
/*
* Making this config "0" means FSP won't set the FLOCKDN bit