diff --git a/src/southbridge/intel/lynxpoint/me.c b/src/southbridge/intel/lynxpoint/me.c
index b56d1d8871..9196fb3d8b 100644
--- a/src/southbridge/intel/lynxpoint/me.c
+++ b/src/southbridge/intel/lynxpoint/me.c
@@ -596,9 +596,9 @@ static int me_icc_set_clock_enables(u32 mask)
 }
 
 /* Determine the path that we should take based on ME status */
-static me_bios_path intel_me_path(struct device *dev)
+static enum me_bios_path intel_me_path(struct device *dev)
 {
-	me_bios_path path = ME_DISABLE_BIOS_PATH;
+	enum me_bios_path path = ME_DISABLE_BIOS_PATH;
 	struct me_hfs hfs;
 	struct me_hfs2 hfs2;
 
@@ -879,7 +879,7 @@ mbp_failure:
 static void intel_me_init(struct device *dev)
 {
 	struct southbridge_intel_lynxpoint_config *config = dev->chip_info;
-	me_bios_path path = intel_me_path(dev);
+	enum me_bios_path path = intel_me_path(dev);
 	struct me_bios_payload mbp_data;
 
 	/* Do initial setup and determine the BIOS path */
diff --git a/src/southbridge/intel/lynxpoint/me.h b/src/southbridge/intel/lynxpoint/me.h
index dfc8a5642f..cf797f3d3e 100644
--- a/src/southbridge/intel/lynxpoint/me.h
+++ b/src/southbridge/intel/lynxpoint/me.h
@@ -303,14 +303,14 @@ struct me_global_reset {
 	u8 reset_type;
 } __packed;
 
-typedef enum {
+enum me_bios_path {
 	ME_NORMAL_BIOS_PATH,
 	ME_S3WAKE_BIOS_PATH,
 	ME_ERROR_BIOS_PATH,
 	ME_RECOVERY_BIOS_PATH,
 	ME_DISABLE_BIOS_PATH,
 	ME_FIRMWARE_UPDATE_BIOS_PATH,
-} me_bios_path;
+};
 
 /* Defined in me_status.c for both romstage and ramstage */
 void intel_me_status(struct me_hfs *hfs, struct me_hfs2 *hfs2);