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sb/intel/i82801gx: Use "sb/intel/common/tco.h" macros 

Also, use {read,write}_pmbase16() in lpc.c file instead of inw/out.

Change-Id: Id281a3478051c4876ccbe26452d8744769c86654
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69878
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2022-11-22 10:43:32 +01:00 committed by Martin L Roth
parent 0f633f7f7f
commit 9f0e21a4da
3 changed files with 7 additions and 8 deletions
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9
src/southbridge/intel/i82801gx/early_init.c
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@ -6,6 +6,7 @@
#include <southbridge/intel/common/gpio.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/rcba.h>
#include <southbridge/intel/common/tco.h>
#include "chip.h"
#include "i82801gx.h"
@ -57,8 +58,6 @@ void i82801gx_setup_bars(void)
pci_write_config8(d31f0, GPIO_CNTL, GPIO_EN);
}
#define TCO_BASE 0x60
#if ENV_RAMINIT
void i82801gx_early_init(void)
{
@ -72,9 +71,9 @@ void i82801gx_early_init(void)
printk(BIOS_DEBUG, "Disabling Watchdog reboot...");
RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */
write_pmbase16(TCO_BASE + 0x8, (1 << 11)); /* halt timer */
write_pmbase16(TCO_BASE + 0x4, (1 << 3)); /* clear timeout */
write_pmbase16(TCO_BASE + 0x6, (1 << 1)); /* clear 2nd timeout */
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, TCO_TMR_HLT);
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_STS, TCO1_TIMEOUT);
write_pmbase16(PMBASE_TCO_OFFSET + TCO2_STS, SECOND_TO_STS);
printk(BIOS_DEBUG, " done.\n");
/* program secondary mlt XXX byte? */

1
src/southbridge/intel/i82801gx/i82801gx.h
View File

@ -320,7 +320,6 @@ void ich7_setup_cir(void);
#define DEVACT_STS 0x44
#define SS_CNT 0x50
#define C3_RES 0x54
#define TCO1_CNT 0x68
#endif /* __ACPI__ */
#endif /* SOUTHBRIDGE_INTEL_I82801GX_I82801GX_H */

5
src/southbridge/intel/i82801gx/lpc.c
View File

@ -20,6 +20,7 @@
#include <southbridge/intel/common/hpet.h>
#include <southbridge/intel/common/pmbase.h>
#include <southbridge/intel/common/spi.h>
#include <southbridge/intel/common/tco.h>
#include "chip.h"
#include "i82801gx.h"
@ -440,9 +441,9 @@ static void lpc_final(struct device *dev)
pci_or_config16(dev, GEN_PMCON_1, 1 << 4);
/* TCO_Lock */
tco1_cnt = inw(DEFAULT_PMBASE + 0x60 + TCO1_CNT);
tco1_cnt = read_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT);
tco1_cnt |= (1 << 12); /* TCO lock */
outw(tco1_cnt, DEFAULT_PMBASE + 0x60 + TCO1_CNT);
write_pmbase16(PMBASE_TCO_OFFSET + TCO1_CNT, tco1_cnt);
/* Indicate finalize step with post code */
post_code(POST_OS_BOOT);