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northbridge/intel/sandybridge: Fix random raminit failures 

Issue observed:
    Intel raminit works in about 50% of all test-cases on lenovo x220.

Problem solution:
    Prefer a smaller valid value over the measured one for
    initial timB timings.

Final testing result:
    Tests on x220 shows that the issue was resolved.
    The test system booted successfully ten times in a row.
    Tests on Gigabyte GA-B75M-D3H revealed no regressions.

Test system:
    * Intel Pentium CPU G2130
    * Gigabyte GA-B75M-D3H
    * DIMM: "Crucial 2GB 256Mx64 CT2566aBA160BJ"

Change-Id: I1a115a45d5febf351d89721ece79eaf43f7ee8a0
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11248
Tested-by: build bot (Jenkins)
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
This commit is contained in:
Patrick Rudolph 2015-08-17 19:24:12 +02:00 committed by Nico Huber
parent 7dcf9d51e5
commit 9f1fbb9a30
1 changed files with 11 additions and 1 deletions
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12
src/northbridge/intel/sandybridge/raminit.c
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@ -2262,7 +2262,17 @@ static void discover_timB(ramctr_timing * ctrl, int channel, int slotrank)
}
FOR_ALL_LANES {
struct run rn = get_longest_zero_run(statistics[lane], 128);
ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
if (rn.start < rn.middle) {
ctrl->timings[channel][slotrank].lanes[lane].timB = rn.start;
} else {
/* In this case statistics[lane][7f] and statistics[lane][0] are
* both zero.
* Prefer a smaller value over rn.start to prevent failures in
* the following write tests.
*/
ctrl->timings[channel][slotrank].lanes[lane].timB = 0;
}
if (rn.all)
die("timB discovery failed");
printram("Bval: %d, %d, %d, %x\n", channel, slotrank,