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soc/intel/apollolake: Add bits of GEN_PMCON2 register 

The values in this patch were found in the following datasheets:
* 334819 (APL)
* 336561 (GLK)

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie7d40395d754b2abdf9079d6ee5e8ab8c536d449
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67661
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Sean Rhodes 2022-09-15 12:12:43 +01:00 committed by Paul Fagerburg
parent 7ef5376123
commit 9f44a8cc39
1 changed files with 5 additions and 0 deletions
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5
src/soc/intel/apollolake/include/soc/pm.h
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@ -165,6 +165,11 @@
WARM_RESET_STS | GLOBAL_RESET_STS | \ WARM_RESET_STS | GLOBAL_RESET_STS | \
SRS | MS4V) SRS | MS4V)
#define GEN_PMCON2 0x1024 #define GEN_PMCON2 0x1024
# define LPC_LPB_CLK_CTRL ((1 << 11) | (1 << 12) | (1 << 13))
# define BIOS_PCI_EXP_EN (1 << 10)
# define PWRBTN_LVL (1 << 9)
# define SMI_LOCK (1 << 4)
# define PER_SMI_SEL (1 << 0)
#define GEN_PMCON3 0x1028 #define GEN_PMCON3 0x1028
# define SLP_S3_ASSERT_WIDTH_SHIFT 10 # define SLP_S3_ASSERT_WIDTH_SHIFT 10
# define SLP_S3_ASSERT_MASK (0x3 << SLP_S3_ASSERT_WIDTH_SHIFT) # define SLP_S3_ASSERT_MASK (0x3 << SLP_S3_ASSERT_WIDTH_SHIFT)