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mb/google/zork: Move PCIE_RST1_L deassertion to happen early for dalboz 

This change moves PCIE_RST1_L deassertion to happen as part of
variant_pcie_power_reset_configure() instead of
variant_romstage_entry() since romstage is guaranteed to run 100ms+
after PP3300_NVME is enabled. This is one of the first things that
coreboot on x86 does as part of early mainboard configuration.

Additionally, this change also drops deassertion of PCIE_RST0_L on bid
1 for dalboz since PCIE_RST0_L is already deasserted much earlier in
the boot flow.

BUG=b:152582706

Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib734aa6ff664268e68388b1997ddce676504f8d2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2261996
Reviewed-by: Aaron Durbin <adurbin@google.com>
Commit-Queue: Aaron Durbin <adurbin@google.com>
Tested-by: Aaron Durbin <adurbin@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/42936
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Furquan Shaikh 2020-06-24 00:03:06 -07:00
parent 7340efcf19
commit 9f47a053a3
3 changed files with 3 additions and 27 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/zork/variants/baseboard/gpio_baseboard_dalboz.c
View File

@ -268,6 +268,9 @@ __weak void variant_pcie_power_reset_configure(void)
{
uint32_t board_version;
/* Deassert PCIE_RST1_L */
gpio_set(GPIO_27, 1);
if (!google_chromeec_cbi_get_board_version(&board_version) &&
(board_version >= CONFIG_VARIANT_MIN_BOARD_ID_V3_SCHEMATICS))
wifi_power_reset_configure_v3();

2
src/mainboard/google/zork/variants/dalboz/Makefile.inc
View File

@ -2,7 +2,5 @@
subdirs-y += ./spd
romstage-y += romstage.c
ramstage-y += gpio.c
ramstage-y += variant.c

25
src/mainboard/google/zork/variants/dalboz/romstage.c
View File

@ -1,25 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
#include <stddef.h>
#include <soc/romstage.h>
#include <baseboard/variants.h>
#include <ec/google/chromeec/ec.h>
#include <gpio.h>
#include <soc/gpio.h>
#include <variant/gpio.h>
void variant_romstage_entry(void)
{
uint32_t board_version;
if (google_chromeec_cbi_get_board_version(&board_version))
board_version = 1;
if (board_version < 2) {
/* SET PCIE_RST0_L HIGH */
gpio_set(WIFI_PCIE_RESET_L, 1);
} else {
/* SET PCIE_RST1_L HIGH */
gpio_set(PCIE_RST1_L, 1);
}
}