diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 9308ed521b..ccf240372c 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -680,7 +680,7 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg,
 	};
 	iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence));
 
-	iosav_run_once(channel);
+	iosav_run_once_and_wait(channel);
 }
 
 /* Obtain optimal power down mode for current configuration */
@@ -1332,7 +1332,7 @@ int receive_enable_calibration(ramctr_timing *ctrl)
 
 		iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 0);
 
-		iosav_run_once(channel);
+		iosav_run_once_and_wait(channel);
 
 		const union gdcr_training_mod_reg training_mod = {
 			.receive_enable_mode = 1,
@@ -1460,7 +1460,7 @@ static int tx_dq_write_leveling(ramctr_timing *ctrl, int channel, int slotrank)
 
 	iosav_write_prea_sequence(channel, slotrank, ctrl->tRP, 18);
 
-	iosav_run_once(channel);
+	iosav_run_once_and_wait(channel);
 
 	for (tx_dq = 0; tx_dq <= MAX_TX_DQ; tx_dq++) {
 		FOR_ALL_LANES ctrl->timings[channel][slotrank].lanes[lane].tx_dq = tx_dq;
diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h
index 3de29ffde6..53d0cd94ef 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.h
+++ b/src/northbridge/intel/sandybridge/raminit_common.h
@@ -291,7 +291,6 @@ typedef struct ramctr_timing_st ramctr_timing;
 
 void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length);
 void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer);
-void iosav_run_once(const int ch);
 void wait_for_iosav(int channel);
 void iosav_run_once_and_wait(const int ch);
 
diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c
index b3c6db6f78..cb49e0ce0e 100644
--- a/src/northbridge/intel/sandybridge/raminit_iosav.c
+++ b/src/northbridge/intel/sandybridge/raminit_iosav.c
@@ -36,11 +36,6 @@ void iosav_run_queue(const int ch, const u8 loops, const u8 as_timer)
 	MCHBAR32(IOSAV_SEQ_CTL_ch(ch)) = loops | ((ssq_count - 1) << 18) | (as_timer << 22);
 }
 
-void iosav_run_once(const int ch)
-{
-	iosav_run_queue(ch, 1, 0);
-}
-
 void wait_for_iosav(int channel)
 {
 	while (1) {
@@ -51,7 +46,7 @@ void wait_for_iosav(int channel)
 
 void iosav_run_once_and_wait(const int ch)
 {
-	iosav_run_once(ch);
+	iosav_run_queue(ch, 1, 0);
 	wait_for_iosav(ch);
 }