From 9f53477768156bfe29403f6facc10552e53a2d64 Mon Sep 17 00:00:00 2001
From: Jonathan Zhang <jonzhang@fb.com>
Date: Mon, 22 Mar 2021 16:23:38 -0700
Subject: [PATCH] soc/intel/fsp_broadwell_de: Set up LPC Generic Memory Range
 register

If mainboard devicetree config defines lpc_lgmr, use it to
set up LPC Generic Memory Range register. Also set up
64KiB memory resource.

Signed-off-by: Jonathan Zhang <jonzhang@fb.com>
Change-Id: Iec94f7364c332789f75c2562e910ea5db4ffad23
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51717
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
---
 src/soc/intel/fsp_broadwell_de/chip.h         |  2 ++
 src/soc/intel/fsp_broadwell_de/southcluster.c | 12 ++++++++++++
 2 files changed, 14 insertions(+)

diff --git a/src/soc/intel/fsp_broadwell_de/chip.h b/src/soc/intel/fsp_broadwell_de/chip.h
index bf2896238a..95c1c2d959 100644
--- a/src/soc/intel/fsp_broadwell_de/chip.h
+++ b/src/soc/intel/fsp_broadwell_de/chip.h
@@ -25,6 +25,8 @@
 struct soc_intel_fsp_broadwell_de_config {
 	/* PCIe completion timeout value */
 	int pcie_compltoval;
+	/* LPC Generic Memory Range Register value */
+	uint32_t lpc_lgmr;
 };
 
 typedef struct soc_intel_fsp_broadwell_de_config config_t;
diff --git a/src/soc/intel/fsp_broadwell_de/southcluster.c b/src/soc/intel/fsp_broadwell_de/southcluster.c
index fb8af87b62..df562f133d 100644
--- a/src/soc/intel/fsp_broadwell_de/southcluster.c
+++ b/src/soc/intel/fsp_broadwell_de/southcluster.c
@@ -28,6 +28,7 @@
 #include <pc80/i8259.h>
 #include <pc80/isa-dma.h>
 #include <soc/iomap.h>
+#include <soc/intel/common/block/lpc/lpc_def.h>
 #include <soc/irq.h>
 #include <soc/lpc.h>
 #include <soc/pci_devs.h>
@@ -216,6 +217,17 @@ static void sc_read_resources(struct device *dev)
 	pci_dev_read_resources(dev);
 	sc_add_mmio_resources(dev);
 	sc_add_io_resources(dev);
+
+	const config_t *config = config_of_soc();
+	if (config->lpc_lgmr) {
+		struct resource *res;
+		res = new_resource(dev, LGMR);
+		res->base = config->lpc_lgmr & ~(LPC_LGMR_EN);
+		res->size = 64 * KiB;
+		res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED
+			| IORESOURCE_RESERVE;
+		pci_write_config32(dev, LGMR, config->lpc_lgmr);
+	}
 }
 
 static void sc_init(struct device *dev)