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lynxpoint: Factor out PIRQ routing from devicetree 

All boards disable PIRQs. They aren't used on modern OSes anyway.

Change-Id: I1351fd4a3910e8cf2e9afe51dc2e82c7464de403
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Angel Pons 2020-07-25 14:03:40 +02:00
parent 172bcc835f
commit 9f78127b61
9 changed files with 16 additions and 88 deletions
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8
src/mainboard/asrock/b85m_pro4/devicetree.cb
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@ -27,14 +27,6 @@ chip northbridge/intel/haswell
chip southbridge/intel/lynxpoint chip southbridge/intel/lynxpoint
register "gen1_dec" = "0x000c0291" # Super I/O HWM register "gen1_dec" = "0x000c0291" # Super I/O HWM
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
register "sata_ahci" = "1" register "sata_ahci" = "1"
register "sata_port_map" = "0x3f" register "sata_port_map" = "0x3f"

9
src/mainboard/asrock/h81m-hds/devicetree.cb
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@ -35,15 +35,6 @@ chip northbridge/intel/haswell
end end
chip southbridge/intel/lynxpoint chip southbridge/intel/lynxpoint
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
register "sata_ahci" = "1" register "sata_ahci" = "1"
register "sata_port_map" = "0x33" register "sata_port_map" = "0x33"

9
src/mainboard/google/beltino/devicetree.cb
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@ -36,15 +36,6 @@ chip northbridge/intel/haswell
device pci 03.0 on end # mini-hd audio device pci 03.0 on end # mini-hd audio
chip southbridge/intel/lynxpoint chip southbridge/intel/lynxpoint
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# SuperIO range is 0x700-0x73f # SuperIO range is 0x700-0x73f
register "gen2_dec" = "0x003c0701" register "gen2_dec" = "0x003c0701"

9
src/mainboard/google/slippy/devicetree.cb
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@ -40,15 +40,6 @@ chip northbridge/intel/haswell
device pci 03.0 on end # mini-hd audio device pci 03.0 on end # mini-hd audio
chip southbridge/intel/lynxpoint chip southbridge/intel/lynxpoint
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# EC range is 0x800-0x9ff # EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801" register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901" register "gen2_dec" = "0x00fc0901"

9
src/mainboard/intel/baskingridge/devicetree.cb
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@ -32,15 +32,6 @@ chip northbridge/intel/haswell
device pci 02.0 on end # vga controller device pci 02.0 on end # vga controller
chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH chip southbridge/intel/lynxpoint # Intel Series 8 Lynx Point PCH
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
# GPI routing # GPI routing
# 0 No effect (default) # 0 No effect (default)
# 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set) # 1 SMI# (if corresponding ALT_GPI_SMI_EN bit is also set)

8
src/mainboard/lenovo/t440p/devicetree.cb
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@ -38,14 +38,6 @@ chip northbridge/intel/haswell
register "gen4_dec" = "0x000c06a1" register "gen4_dec" = "0x000c06a1"
register "gpi13_routing" = "2" register "gpi13_routing" = "2"
register "gpi1_routing" = "2" register "gpi1_routing" = "2"
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
register "sata_ahci" = "1" register "sata_ahci" = "1"
# 0(HDD), 1(M.2), 5(ODD) # 0(HDD), 1(M.2), 5(ODD)
register "sata_port_map" = "0x23" register "sata_port_map" = "0x23"

9
src/mainboard/supermicro/x10slm-f/devicetree.cb
View File

@ -26,15 +26,6 @@ chip northbridge/intel/haswell
device pci 03.0 off end # Mini-HD audio device pci 03.0 off end # Mini-HD audio
chip southbridge/intel/lynxpoint chip southbridge/intel/lynxpoint
register "pirqa_routing" = "0x80"
register "pirqb_routing" = "0x80"
register "pirqc_routing" = "0x80"
register "pirqd_routing" = "0x80"
register "pirqe_routing" = "0x80"
register "pirqf_routing" = "0x80"
register "pirqg_routing" = "0x80"
register "pirqh_routing" = "0x80"
register "sata_ahci" = "1" register "sata_ahci" = "1"
register "sata_port_map" = "0x3f" register "sata_port_map" = "0x3f"

13
src/southbridge/intel/lynxpoint/chip.h
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@ -6,19 +6,6 @@
#include <stdint.h> #include <stdint.h>
struct southbridge_intel_lynxpoint_config { struct southbridge_intel_lynxpoint_config {
/**
* Interrupt Routing configuration
* If bit7 is 1, the interrupt is disabled.
*/
uint8_t pirqa_routing;
uint8_t pirqb_routing;
uint8_t pirqc_routing;
uint8_t pirqd_routing;
uint8_t pirqe_routing;
uint8_t pirqf_routing;
uint8_t pirqg_routing;
uint8_t pirqh_routing;
/** /**
* GPI Routing configuration for LynxPoint-H * GPI Routing configuration for LynxPoint-H
* *

30
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -96,18 +96,18 @@ static void pch_enable_serial_irqs(struct device *dev)
static void pch_pirq_init(struct device *dev) static void pch_pirq_init(struct device *dev)
{ {
struct device *irq_dev; struct device *irq_dev;
/* Get the chip configuration */
config_t *config = dev->chip_info;
pci_write_config8(dev, PIRQA_ROUT, config->pirqa_routing); const uint8_t pirq = 0x80;
pci_write_config8(dev, PIRQB_ROUT, config->pirqb_routing);
pci_write_config8(dev, PIRQC_ROUT, config->pirqc_routing);
pci_write_config8(dev, PIRQD_ROUT, config->pirqd_routing);
pci_write_config8(dev, PIRQE_ROUT, config->pirqe_routing); pci_write_config8(dev, PIRQA_ROUT, pirq);
pci_write_config8(dev, PIRQF_ROUT, config->pirqf_routing); pci_write_config8(dev, PIRQB_ROUT, pirq);
pci_write_config8(dev, PIRQG_ROUT, config->pirqg_routing); pci_write_config8(dev, PIRQC_ROUT, pirq);
pci_write_config8(dev, PIRQH_ROUT, config->pirqh_routing); pci_write_config8(dev, PIRQD_ROUT, pirq);
pci_write_config8(dev, PIRQE_ROUT, pirq);
pci_write_config8(dev, PIRQF_ROUT, pirq);
pci_write_config8(dev, PIRQG_ROUT, pirq);
pci_write_config8(dev, PIRQH_ROUT, pirq);
/* Eric Biederman once said we should let the OS do this. /* Eric Biederman once said we should let the OS do this.
* I am not so sure anymore he was right. * I am not so sure anymore he was right.
@ -122,10 +122,12 @@ static void pch_pirq_init(struct device *dev)
int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN);
switch (int_pin) { switch (int_pin) {
case 1: /* INTA# */ int_line = config->pirqa_routing; break; case 1: /* INTA# */
case 2: /* INTB# */ int_line = config->pirqb_routing; break; case 2: /* INTB# */
case 3: /* INTC# */ int_line = config->pirqc_routing; break; case 3: /* INTC# */
case 4: /* INTD# */ int_line = config->pirqd_routing; break; case 4: /* INTD# */
int_line = pirq;
break;
} }
if (!int_line) if (!int_line)