diff --git a/src/northbridge/intel/haswell/acpi/hostbridge.asl b/src/northbridge/intel/haswell/acpi/hostbridge.asl
index d0faa7931c..32e2998850 100644
--- a/src/northbridge/intel/haswell/acpi/hostbridge.asl
+++ b/src/northbridge/intel/haswell/acpi/hostbridge.asl
@@ -1,7 +1,5 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
-#include "../haswell.h"
-
 Name (_HID, EISAID ("PNP0A08"))	// PCIe
 Name (_CID, EISAID ("PNP0A03"))	// PCI
 
diff --git a/src/northbridge/intel/haswell/haswell.h b/src/northbridge/intel/haswell/haswell.h
index 16a4ec4f43..b010cdfbd0 100644
--- a/src/northbridge/intel/haswell/haswell.h
+++ b/src/northbridge/intel/haswell/haswell.h
@@ -3,21 +3,18 @@
 #ifndef __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
 #define __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__
 
-/* Chipset types */
-#define HASWELL_MOBILE	0
-#define HASWELL_DESKTOP	1
-#define HASWELL_SERVER	2
+#include <device/device.h>
+#include <northbridge/intel/common/fixed_bars.h>
 
 #include "memmap.h"
-
-/* Everything below this line is ignored in the DSDT */
-#ifndef __ACPI__
+#include "registers/dmibar.h"
+#include "registers/epbar.h"
+#include "registers/host_bridge.h"
+#include "registers/mchbar.h"
 
 /* Device 0:0.0 PCI configuration space (Host Bridge) */
 #define HOST_BRIDGE	PCI_DEV(0, 0, 0)
 
-#include "registers/host_bridge.h"
-
 /* Device 0:1.0 PCI configuration space (PCIe Graphics) */
 
 #define PEG_CAP		0xa2
@@ -51,15 +48,6 @@
 
 #define MSAC		0x62	/* Multi Size Aperture Control */
 
-/*
- * MCHBAR
- */
-
-#include <northbridge/intel/common/fixed_bars.h>
-
-/* As there are many registers, define them on a separate file */
-#include "registers/mchbar.h"
-
 #define ARCHDIS		0xff0	/* DMA Remap Engine Policy Control */
 #define  DMAR_LCKDN	(1 << 31)
 #define  SPCAPCTRL	(1 << 25)
@@ -68,20 +56,6 @@
 #define  GLBIOTLBINV	(1 << 1)
 #define  GLBCTXTINV	(1 << 0)
 
-/*
- * EPBAR - Egress Port Root Complex Register Block
- */
-
-#include "registers/epbar.h"
-
-/*
- * DMIBAR
- */
-
-#include "registers/dmibar.h"
-
-#ifndef __ASSEMBLER__
-
 void mb_late_romstage_setup(void); /* optional */
 
 void haswell_early_initialization(void);
@@ -90,12 +64,8 @@ void haswell_unhide_peg(void);
 
 void report_platform_info(void);
 
-#include <device/device.h>
-
 struct acpi_rsdp;
 unsigned long northbridge_write_acpi_tables(const struct device *device, unsigned long start,
 					    struct acpi_rsdp *rsdp);
 
-#endif /* __ASSEMBLER__ */
-#endif /* __ACPI__ */
 #endif /* __NORTHBRIDGE_INTEL_HASWELL_HASWELL_H__ */