nb/intel/x4x: Fix memory hole with both channels populated
Previously, 0xa0000000 to 0xc0000000 needed to be reserved as a non-usable memory hole because it would hang on memory i/o. Memtest86+ now passes with no errors on both channels populated. Tested on GA-G41M-ES2L with 2x2GiB sticks of ram. Change-Id: Ib52a63a80f5f69c16841f10ddb896ab3c7d30462 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/13125 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
This commit is contained in:
Damien Zammit
Martin Roth
parent
43f16f8dd8
commit
9fb08f55a8
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@ -26,25 +26,24 @@
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#include <cpu/cpu.h>
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#include <boot/tables.h>
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#include <arch/acpi.h>
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#include <northbridge/intel/x4x/iomap.h>
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#include <northbridge/intel/x4x/chip.h>
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#include <northbridge/intel/x4x/x4x.h>
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/* Reserve segments A and B:
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*
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* 0xa0000 - 0xbffff: legacy VGA
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*/
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static const int legacy_hole_base_k = 0xa0000 / 1024;
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static const int legacy_hole_size_k = 128;
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#include <cbmem.h>
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static void mch_domain_read_resources(device_t dev)
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{
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u8 index;
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u64 tom, touud;
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u32 tomk, tsegk, tolud, usable_tomk;
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u32 tomk, tseg_sizek, tolud, usable_tomk;
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u32 pcie_config_base, pcie_config_size;
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u32 uma_sizek = 0;
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const u32 top32memk = 4 * (GiB / KiB);
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index = 3;
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/* 1024KiB TSEG */
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tsegk = 1 << 10;
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tseg_sizek = 1024;
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pci_domain_read_resources(dev);
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@ -77,53 +76,52 @@ static void mch_domain_read_resources(device_t dev)
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const u32 gsm_sizek = decode_igd_gtt_size((ggc >> 8) & 0xf);
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printk(BIOS_DEBUG, " and %uM GTT\n", gsm_sizek >> 10);
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uma_sizek = gms_sizek + gsm_sizek + tsegk;
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uma_sizek = gms_sizek + gsm_sizek + tseg_sizek;
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usable_tomk = tomk - uma_sizek;
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printk(BIOS_INFO, "Available memory below 4GB: %uM\n", usable_tomk >> 10);
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/* Report the memory regions */
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ram_resource(dev, 3, 0, legacy_hole_base_k);
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ram_resource(dev, 4, legacy_hole_base_k + legacy_hole_size_k,
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(usable_tomk - (legacy_hole_base_k + legacy_hole_size_k)));
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ram_resource(dev, index++, 0, 0xa0000 >> 10);
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ram_resource(dev, index++, 1*MiB >> 10, (usable_tomk - (1*MiB >> 10)));
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/*
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* If >= 4GB installed then memory from TOLUD to 4GB
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* is remapped above TOM, TOUUD will account for both
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*/
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touud >>= 10; /* Convert to KB */
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if (touud > 4096 * 1024) {
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ram_resource(dev, 5, 4096 * 1024, touud - (4096 * 1024));
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if (touud > top32memk) {
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ram_resource(dev, index++, top32memk, touud - top32memk);
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printk(BIOS_INFO, "Available memory above 4GB: %lluM\n",
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(touud >> 10) - 4096);
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(touud - top32memk) >> 10);
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}
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printk(BIOS_DEBUG, "Adding UMA memory area base=0x%08x "
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"size=0x%08x\n", usable_tomk << 10, uma_sizek << 10);
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fixed_mem_resource(dev, 6, usable_tomk, uma_sizek, IORESOURCE_RESERVE);
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"size=0x%08x\n", usable_tomk << 10, uma_sizek << 10);
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fixed_mem_resource(dev, index++, usable_tomk, uma_sizek,
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IORESOURCE_RESERVE);
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/* Some strange hole, reserve it */
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//fixed_mem_resource(dev, 7, usable_tomk - (0x02000000 >> 10), 0x02000000 >> 10, IORESOURCE_RESERVE);
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/* Reserve high memory where the NB BARs are up to 4GiB */
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fixed_mem_resource(dev, index++, DEFAULT_HECIBAR >> 10,
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top32memk - (DEFAULT_HECIBAR >> 10),
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IORESOURCE_RESERVE);
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if (decode_pciebar(&pcie_config_base, &pcie_config_size)) {
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printk(BIOS_DEBUG, "Adding PCIe config bar base=0x%08x "
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"size=0x%x\n", pcie_config_base, pcie_config_size);
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fixed_mem_resource(dev, 7, pcie_config_base >> 10,
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fixed_mem_resource(dev, index++, pcie_config_base >> 10,
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pcie_config_size >> 10, IORESOURCE_RESERVE);
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}
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set_top_of_ram(usable_tomk * 1024);
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}
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static void mch_domain_set_resources(device_t dev)
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{
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struct resource *resource;
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int i;
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struct resource *res;
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for (i = 3; i < 8; ++i) {
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/* Report read resources. */
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resource = probe_resource(dev, i);
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if (resource)
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report_resource_stored(dev, resource, "");
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}
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for (res = dev->resource_list; res; res = res->next)
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report_resource_stored(dev, res, "");
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assign_resources(dev->link_list);
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}
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@ -141,10 +139,9 @@ static void mch_domain_init(device_t dev)
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static struct device_operations pci_domain_ops = {
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.read_resources = mch_domain_read_resources,
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.set_resources = mch_domain_set_resources,
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.enable_resources = NULL,
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.init = mch_domain_init,
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.scan_bus = pci_domain_scan_bus,
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.ops_pci_bus = pci_bus_default_ops,
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.ops_pci_bus = pci_bus_default_ops,
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.write_acpi_tables = northbridge_write_acpi_tables,
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.acpi_fill_ssdt_generator = generate_cpu_entries,
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};
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@ -160,7 +157,6 @@ static struct device_operations cpu_bus_ops = {
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.set_resources = DEVICE_NOOP,
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.enable_resources = DEVICE_NOOP,
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.init = cpu_bus_init,
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.scan_bus = 0,
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};
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@ -23,6 +23,8 @@
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#include "iomap.h"
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#include "x4x.h"
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#define ME_UMA_SIZEMB 0
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static inline void barrier(void)
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{
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asm volatile("mfence":::);
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@ -1465,7 +1467,8 @@ static void dradrb_ddr2(struct sysinfo *s)
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u32 dra0;
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u32 dra1;
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u16 totalmemorymb;
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u16 size, offset;
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u32 size, offset;
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u32 size0, size1;
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u8 dratab[2][2][2][4] = {
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{
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{
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@ -1562,35 +1565,51 @@ static void dradrb_ddr2(struct sysinfo *s)
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MCHBAR16(0x606 + 2*msbpos(rankpop1)) = c0drb + c1drb;
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}
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MCHBAR8(0x111) = MCHBAR8(0x111) | 0x2;
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MCHBAR16(0x104) = 0;
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size = s->channel_capacity[0] + s->channel_capacity[1];
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MCHBAR16(0x102) = size;
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/* Populated channel sizes in MiB */
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size0 = s->channel_capacity[0];
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size1 = s->channel_capacity[1];
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MCHBAR8(0x111) = MCHBAR8(0x111) & ~0x2;
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MCHBAR8(0x111) = MCHBAR8(0x111) | (1 << 4);
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/* Set ME UMA size in MiB */
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MCHBAR16(0x100) = ME_UMA_SIZEMB;
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/* Set ME UMA Present bit */
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MCHBAR32(0x111) = MCHBAR32(0x111) | 1;
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size = MIN(size0 - ME_UMA_SIZEMB, size1) * 2;
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MCHBAR16(0x104) = size;
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MCHBAR16(0x102) = size0 + size1 - size;
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map = 0;
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if (s->channel_capacity[0] == 0) {
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if (size0 == 0) {
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map = 0;
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} else if (s->channel_capacity[1] == 0) {
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} else if (size1 == 0) {
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map |= 0x20;
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} else {
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map |= 0x40;
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}
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map |= 0x18;
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if (s->channel_capacity[0] <= s->channel_capacity[1]) {
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map |= 0x5;
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} else if (s->channel_capacity[0] > s->channel_capacity[1]) {
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if (size == 0) {
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map |= 0x18;
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}
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if (size0 - ME_UMA_SIZEMB >= size1) {
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map |= 0x4;
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}
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MCHBAR8(0x110) = map;
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MCHBAR16(0x10e) = 0;
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if (s->channel_capacity[1] != 0) {
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if (size1 != 0) {
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offset = 0;
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} else if (s->channel_capacity[0] > s->channel_capacity[1]) {
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offset = size;
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} else if ((size0 > size1) && ((map & 0x7) == 0x4)) {
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offset = size/2 + (size0 + size1 - size);
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} else {
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offset = 0;
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offset = size/2 + ME_UMA_SIZEMB;
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}
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MCHBAR16(0x108) = offset;
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MCHBAR16(0x10a) = 0;
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MCHBAR16(0x10a) = size/2;
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}
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static void mmap_ddr2(struct sysinfo *s)
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@ -1605,7 +1624,7 @@ static void mmap_ddr2(struct sysinfo *s)
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gttsize = ggc2gtt[(ggc & 0xf00) >> 8];
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tsegsize = 1; // 1MB TSEG
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mmiosize = 0x400; // 1GB MMIO
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tom = s->channel_capacity[0] + s->channel_capacity[1];
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tom = s->channel_capacity[0] + s->channel_capacity[1] - ME_UMA_SIZEMB;
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tolud = MIN(0x1000 - mmiosize, tom);
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touud = tom;
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gfxbase = tolud - gfxsize;
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