diff --git a/payloads/libpayload/arch/x86/apic.c b/payloads/libpayload/arch/x86/apic.c
index 079f456eec..99eff27aad 100644
--- a/payloads/libpayload/arch/x86/apic.c
+++ b/payloads/libpayload/arch/x86/apic.c
@@ -210,6 +210,8 @@ static void apic_init_timer(void)
 		/* Set APIC init counter to MAX and count for 1 ms */
 		apic_write32(APIC_TIMER_INIT_COUNT, UINT32_MAX);
 
+		/* This is safe because apic_initialized() returns false so
+		 * arch_ndelay() falls back to a busy loop. */
 		mdelay(1);
 
 		ticks_per_ms =
diff --git a/payloads/libpayload/arch/x86/delay.c b/payloads/libpayload/arch/x86/delay.c
index 541cf7a436..19931fbc04 100644
--- a/payloads/libpayload/arch/x86/delay.c
+++ b/payloads/libpayload/arch/x86/delay.c
@@ -28,6 +28,7 @@
  */
 
 #include <libpayload.h>
+#include <arch/apic.h>
 
 /* The pause instruction can delay 10-140 CPU cycles, so avoid calling it when
  * getting close to finishing. Depending on the timer source, the timer can be
@@ -35,12 +36,23 @@
  * that the timer is running at the CPU frequency. */
 #define PAUSE_THRESHOLD_TICKS		150
 
+/* Let's assume APIC interrupts take at least 100us */
+#define APIC_INTERRUPT_LATENCY_NS	(100 * NSECS_PER_USEC)
+
+
 void arch_ndelay(uint64_t ns)
 {
 	uint64_t delta = ns * timer_hz() / NSECS_PER_SEC;
 	uint64_t pause_delta = 0;
+	uint64_t apic_us = 0;
 	uint64_t start = timer_raw_value();
 
+	if (ns > APIC_INTERRUPT_LATENCY_NS)
+		apic_us = (ns - APIC_INTERRUPT_LATENCY_NS) / NSECS_PER_USEC;
+
+	if (IS_ENABLED(CONFIG_LP_ENABLE_APIC) && apic_initialized() && apic_us)
+		apic_delay(apic_us);
+
 	if (delta > PAUSE_THRESHOLD_TICKS)
 		pause_delta = delta - PAUSE_THRESHOLD_TICKS;