GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

baytrail: Add SOC thermal settings 

Apply the SOC thermal settings from DPTF reference code for
SdpProfile=4 and adjust graphics PUNIT setting to match.

BUG=chrome-os-partner:17279
BRANCH=baytrail
TEST=boot on rambi and check for valid GPU power values from DPTF

Change-Id: I59fc4b75b52084ebcc4c0556563afca0585ea6b8
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182786
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/5052
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Duncan Laurie 2014-01-16 09:47:39 -08:00 committed by Kyösti Mälkki
parent c6313db34f
commit 9fd7c0f18e
4 changed files with 74 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/soc/intel/baytrail/Makefile.inc
View File

@ -44,6 +44,7 @@ ramstage-y += emmc.c
ramstage-y += lpss.c
ramstage-y += pcie.c
ramstage-y += sd.c
ramstage-y += dptf.c
ramstage-y += perf_power.c
ramstage-y += stage_cache.c
romstage-y += stage_cache.c

18
src/soc/intel/baytrail/baytrail/iosf.h
View File

@ -240,6 +240,24 @@ void iosf_ssus_write(int reg, uint32_t val);
#define PUNIT_PWRGT_STATUS 0x61
#define PUNIT_GPU_EC_VIRUS 0xd2
#define PUNIT_SOC_POWER_BUDGET 0x02
#define PUNIT_SOC_ENERGY_CREDIT 0x03
#define PUNIT_PTMC 0x80
#define PUNIT_GFXT 0x88
#define PUNIT_VEDT 0x89
#define PUNIT_ISPT 0x8c
#define PUNIT_PTPS 0xb2
#define PUNIT_TE_AUX0 0xb5
#define PUNIT_TE_AUX1 0xb6
#define PUNIT_TE_AUX2 0xb7
#define PUNIT_TE_AUX3 0xb8
#define PUNIT_TTE_VRIccMax 0xb9
#define PUNIT_TTE_VRHot 0xba
#define PUNIT_TTE_XXPROCHOT 0xbb
#define PUNIT_TTE_SLM0 0xbc
#define PUNIT_TTE_SLM1 0xbd
#define PUNIT_TTE_SWT 0xbf
/*
* LPSS Registers
*/

54
src/soc/intel/baytrail/dptf.c Normal file
View File

@ -0,0 +1,54 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2014 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <stdint.h>
#include <arch/io.h>
#include <bootstate.h>
#include <console/console.h>
#include <reg_script.h>
#include <baytrail/iosf.h>
static const struct reg_script dptf_init_settings[] = {
/* SocThermInit */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTMC, 0x00030708),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GFXT, 0x0000C000),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_VEDT, 0x00000004),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_ISPT, 0x00000004),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_PTPS, 90 << 24), /* Tj_max=90C */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TE_AUX3, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRIccMax, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_VRHot, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_XXPROCHOT, 0x00061029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM0, 0x00001029),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_TTE_SLM1, 0x00001029),
/* ratio 10 = 1333mhz for 2.5W fanless */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_POWER_BUDGET, 0x00000A00),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_SOC_ENERGY_CREDIT, 0x00000002),
REG_SCRIPT_END,
};
static void dptf_init(void *unused)
{
printk(BIOS_DEBUG, "Applying SOC Thermal settings for DPTF.\n");
reg_script_run(dptf_init_settings);
}
BOOT_STATE_INIT_ENTRIES(dptf_init_bscb) = {
BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_ENTRY, dptf_init, NULL),
};

2
src/soc/intel/baytrail/gfx.c
View File

@ -142,7 +142,7 @@ static const struct reg_script gfx_init_script[] = {
/* Program PUNIT_GPU_EC_VIRUS based on DPTF SDP */
/* SDP Profile 4 == 0x11940, others 0xcf08 */
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0xcf08),
REG_IOSF_WRITE(IOSF_PORT_PMC, PUNIT_GPU_EC_VIRUS, 0x11940),
/* GfxPause */
REG_RES_WRITE32(PCI_BASE_ADDRESS_0, 0xa000, 0x00071388),