sandybridge/raminit_common: use MCHBAR AND/OR macros in remaining places
Change-Id: I1c81eb7c8ed0b819bb76196208cc1269180aca55 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/27754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
This commit is contained in:
Felix Held
parent
ff22b6aca6
commit
9fe248fbec
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@ -195,7 +195,7 @@ void dram_xover(ramctr_timing * ctrl)
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static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
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{
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struct cpuid_result cpures;
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u32 reg, addr, cpu, stretch;
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u32 cpu, stretch;
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stretch = ctrl->ref_card_offset[channel];
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/* ODT stretch: Delay ODT signal by stretch value.
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@ -205,19 +205,13 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel)
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if (IS_SANDY_CPU(cpu) && IS_SANDY_CPU_C(cpu)) {
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if (stretch == 2)
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stretch = 3;
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addr = 0x400 * channel + 0x401c;
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reg = MCHBAR32(addr) & 0xffffc3ff;
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reg |= (stretch << 12);
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reg |= (stretch << 10);
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MCHBAR32(addr) = reg;
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MCHBAR32_AND_OR(0x401c + 0x400 * channel, 0xffffc3ff,
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(stretch << 12) | (stretch << 10));
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printram("OTHP Workaround [%x] = %x\n", addr, reg);
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} else {
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// OTHP
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addr = 0x400 * channel + 0x400c;
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reg = MCHBAR32(addr) & 0xfff0ffff;
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reg |= (stretch << 16);
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reg |= (stretch << 18);
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MCHBAR32(addr) = reg;
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MCHBAR32_AND_OR(0x400c + 0x400 * channel, 0xfff0ffff,
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(stretch << 16) | (stretch << 18));
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printram("OTHP [%x] = %x\n", addr, reg);
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}
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}
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@ -262,7 +256,7 @@ void dram_timing_regs(ramctr_timing *ctrl)
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MCHBAR32(0x400 * channel + 0x4014) = 0;
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MCHBAR32(addr) |= 0x00020000;
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MCHBAR32_OR(addr, 0x00020000);
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dram_odt_stretch(ctrl, channel);
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@ -280,7 +274,7 @@ void dram_timing_regs(ramctr_timing *ctrl)
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printram("REFI [%x] = %x\n", 0x400 * channel + 0x4298, reg);
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MCHBAR32(0x400 * channel + 0x4298) = reg;
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MCHBAR32(0x400 * channel + 0x4294) |= 0xff;
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MCHBAR32_OR(0x400 * channel + 0x4294, 0xff);
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// SRFTP
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reg = 0;
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@ -656,7 +650,7 @@ static void write_reset(ramctr_timing * ctrl)
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void dram_jedecreset(ramctr_timing * ctrl)
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{
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u32 reg, addr;
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u32 reg;
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int channel;
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while (!(MCHBAR32(0x5084) & 0x10000));
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@ -672,37 +666,33 @@ void dram_jedecreset(ramctr_timing * ctrl)
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MCHBAR32(0x5030) = reg;
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// Assert dimm reset signal
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reg = MCHBAR32(0x5030);
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reg &= ~0x2;
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MCHBAR32(0x5030) = reg;
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MCHBAR32_AND(0x5030, ~0x2);
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// Wait 200us
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udelay(200);
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// Deassert dimm reset signal
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MCHBAR32(0x5030) |= 2;
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MCHBAR32_OR(0x5030, 2);
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// Wait 500us
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udelay(500);
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// Enable DCLK
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MCHBAR32(0x5030) |= 4;
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MCHBAR32_OR(0x5030, 4);
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// XXX Wait 20ns
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udelay(1);
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FOR_ALL_CHANNELS {
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// Set valid rank CKE
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reg = 0;
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reg = (reg & ~0xf) | ctrl->rankmap[channel];
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addr = 0x400 * channel + 0x42a0;
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MCHBAR32(addr) = reg;
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reg = ctrl->rankmap[channel];
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MCHBAR32(0x42a0 + 0x400 * channel) = reg;
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// Wait 10ns for ranks to settle
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//udelay(0.01);
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reg = (reg & ~0xf0) | (ctrl->rankmap[channel] << 4);
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MCHBAR32(addr) = reg;
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MCHBAR32(0x42a0 + 0x400 * channel) = reg;
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// Write reset using a NOP
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write_reset(ctrl);
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@ -862,7 +852,6 @@ static void dram_mr3(ramctr_timing *ctrl, u8 rank, int channel)
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void dram_mrscommands(ramctr_timing * ctrl)
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{
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u8 slotrank;
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u32 reg, addr;
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int channel;
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FOR_ALL_POPULATED_CHANNELS {
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@ -903,13 +892,10 @@ void dram_mrscommands(ramctr_timing * ctrl)
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}
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// Refresh enable
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MCHBAR32(0x5030) |= 8;
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MCHBAR32_OR(0x5030, 8);
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FOR_ALL_POPULATED_CHANNELS {
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addr = 0x400 * channel + 0x4020;
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reg = MCHBAR32(addr);
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reg &= ~0x200000;
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MCHBAR32(addr) = reg;
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MCHBAR32_AND(0x4020 + 0x400 * channel, ~0x200000);
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wait_428c(channel);
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@ -1478,9 +1464,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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MCHBAR32(0x4230 + 0x400 * channel) =
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(max((ctrl->tFAW >> 2) + 1, ctrl->tRRD) << 10)
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| 4 | (ctrl->tRCD << 16);
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | (6 << 16);
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MCHBAR32(0x4210 + 0x400 * channel) = 0x244;
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/* DRAM command NOP */
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@ -1518,9 +1502,7 @@ static void test_timC(ramctr_timing * ctrl, int channel, int slotrank)
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MCHBAR32(0x4234 + 0x400 * channel) =
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(max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1) << 10)
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| 8 | (ctrl->CAS << 16);
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MCHBAR32(0x4204 + 0x400 * channel) = (slotrank << 24) | 0x60000;
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MCHBAR32(0x4214 + 0x400 * channel) = 0x244;
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/* DRAM command RD */
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@ -1553,7 +1535,7 @@ static int discover_timC(ramctr_timing *ctrl, int channel, int slotrank)
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/* DRAM command PREA */
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MCHBAR32(0x4220 + 0x400 * channel) = 0x1f002;
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MCHBAR32(0x4230 + 0x400 * channel) = 0xc01 | (ctrl->tRP << 16);
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;
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MCHBAR32(0x4200 + 0x400 * channel) = (slotrank << 24) | 0x60400;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x240;
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// execute command queue
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@ -1725,7 +1707,6 @@ static void precharge(ramctr_timing * ctrl)
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MCHBAR32(0x422c + 0x400 * channel) = 0x1f000;
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MCHBAR32(0x423c + 0x400 * channel) =
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0xc01 | (ctrl->tMOD << 16);
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MCHBAR32(0x420c + 0x400 * channel) =
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(slotrank << 24) | 0x360000;
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MCHBAR32(0x421c + 0x400 * channel) = 0;
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@ -2095,11 +2076,10 @@ static int test_320c(ramctr_timing * ctrl, int channel, int slotrank)
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MCHBAR32(0x4230 + 0x400 * channel) =
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((max(ctrl->tRRD, (ctrl->tFAW >> 2) + 1)) << 10)
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| 8 | (ctrl->tRCD << 16);
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MCHBAR32(0x4200 + 0x400 * channel) =
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(slotrank << 24) | ctr | 0x60000;
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MCHBAR32(0x4210 + 0x400 * channel) = 0x244;
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/* DRAM command WR */
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MCHBAR32(0x4224 + 0x400 * channel) = 0x1f201;
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MCHBAR32(0x4234 + 0x400 * channel) =
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@ -3059,7 +3039,7 @@ void prepare_training(ramctr_timing * ctrl)
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FOR_ALL_POPULATED_CHANNELS {
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// Always drive command bus
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MCHBAR32(0x4004 + 0x400 * channel) |= 0x20000000;
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MCHBAR32_OR(0x4004 + 0x400 * channel, 0x20000000);
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}
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udelay(1);
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@ -3170,8 +3150,8 @@ void final_registers(ramctr_timing * ctrl)
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FOR_ALL_CHANNELS
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MCHBAR32_AND_OR(0x4294 + 0x400 * channel, ~0x30000, 1 << 16);
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MCHBAR32(0x5030) |= 1;
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MCHBAR32(0x5030) |= 0x80;
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MCHBAR32_OR(0x5030, 1);
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MCHBAR32_OR(0x5030, 0x80);
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MCHBAR32(0x5f18) = 0xfa;
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/* Find a populated channel. */
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