mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for USB ports

Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4).

BUG=b:199468920
TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement.

Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This commit is contained in:
Kenneth Chan 2021-12-20 12:16:03 +08:00 committed by Felix Held
parent 2ea8b945ec
commit 9fe2ce802a
1 changed files with 40 additions and 0 deletions

View File

@ -18,6 +18,46 @@ chip soc/amd/cezanne
register "telemetry_vddcrsocfull_scale_current_mA" = "30314" #mA register "telemetry_vddcrsocfull_scale_current_mA" = "30314" #mA
register "telemetry_vddcrsocoffset" = "560" register "telemetry_vddcrsocoffset" = "560"
#USB 2.0 phy config
register "usb_phy" = "{
/* Left USB C0 Port */
.Usb2PhyPort[0] = {
.compdstune = 3,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 3,
.txpreemppulsetune = 0,
.txrisetune = 1,
.txvreftune = 6,
.txhsxvtune = 3,
.txrestune = 1,
},
/* Left USB A0 Port */
.Usb2PhyPort[1] = {
.compdstune = 3,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 3,
.txpreemppulsetune = 0,
.txrisetune = 1,
.txvreftune = 6,
.txhsxvtune = 3,
.txrestune = 1,
},
/* Right USB C1 Port */
.Usb2PhyPort[4] = {
.compdstune = 3,
.sqrxtune = 3,
.txfslstune = 3,
.txpreempamptune = 3,
.txpreemppulsetune = 0,
.txrisetune = 1,
.txvreftune = 6,
.txhsxvtune = 3,
.txrestune = 1,
},
}"
# I2C Config # I2C Config
#+-------------------+---------------------------+ #+-------------------+---------------------------+
#| Field | Value | #| Field | Value |