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cpu/intel/fsp_model_406dx: code cleanup 

Code cleanup requested in commit 09670265 -
"cpu/intel: Add fsp version of model 406dx (Rangeley / Atom C2000)"

- add guard statements to chip.h
- remove excessive includes
- whitespace cleanup
- add an IS_ENABLED

Change-Id: Iaa85bd66953df015f083b23f6fd32949bcfd17bc
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/6599
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Martin Roth 2014-08-11 11:47:47 -06:00 committed by Martin Roth
parent 7aa704b822
commit 9ff030fb25
3 changed files with 13 additions and 14 deletions
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5
src/cpu/intel/fsp_model_406dx/chip.h
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@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef CPU_FSP_MODEL406DX_CHIP_H
#define CPU_FSP_MODEL406DX_CHIP_H
/* Magic value used to locate this chip in the device tree */ /* Magic value used to locate this chip in the device tree */
#define SPEEDSTEP_APIC_MAGIC 0xACAC #define SPEEDSTEP_APIC_MAGIC 0xACAC
@ -31,3 +34,5 @@ struct cpu_intel_fsp_model_406dx_config {
int c2_acpower; /* ACPI C2 on AC Power */ int c2_acpower; /* ACPI C2 on AC Power */
int c3_acpower; /* ACPI C3 on AC Power */ int c3_acpower; /* ACPI C3 on AC Power */
}; };
#endif /* CPU_FSP_MODEL406DX_CHIP_H */

2
src/cpu/intel/fsp_model_406dx/model_406dx.h
View File

@ -110,4 +110,4 @@ int cpu_config_tdp_levels(void);
#endif #endif
#endif #endif
#endif #endif /* _CPU_INTEL_MODEL_406DX_H */

20
src/cpu/intel/fsp_model_406dx/model_406dx_init.c
View File

@ -22,19 +22,13 @@
*/ */
#include <console/console.h> #include <console/console.h>
#include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <string.h>
#include <arch/acpi.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>
#include <cpu/x86/mtrr.h> #include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h> #include <cpu/x86/msr.h>
#include <cpu/x86/lapic.h> #include <cpu/x86/lapic.h>
#include <cpu/intel/speedstep.h>
#include <cpu/intel/turbo.h>
#include <cpu/x86/cache.h> #include <cpu/x86/cache.h>
#include <cpu/x86/name.h> #include <cpu/x86/name.h>
#include <pc80/mc146818rtc.h>
#include "model_406dx.h" #include "model_406dx.h"
#include "chip.h" #include "chip.h"
@ -42,7 +36,7 @@ static void enable_vmx(void)
{ {
struct cpuid_result regs; struct cpuid_result regs;
msr_t msr; msr_t msr;
int enable = CONFIG_ENABLE_VMX; int enable = IS_ENABLED(CONFIG_ENABLE_VMX);
regs = cpuid(1); regs = cpuid(1);
/* Check that the VMX is supported before reading or writing the MSR. */ /* Check that the VMX is supported before reading or writing the MSR. */
@ -67,9 +61,9 @@ static void enable_vmx(void)
printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling"); printk(BIOS_DEBUG, "%s VMX\n", enable ? "Enabling" : "Disabling");
if (enable) { if (enable) {
msr.lo |= (1 << 2); msr.lo |= (1 << 2);
if (regs.ecx & CPUID_SMX) if (regs.ecx & CPUID_SMX)
msr.lo |= (1 << 1); msr.lo |= (1 << 1);
} }
wrmsr(IA32_FEATURE_CONTROL, msr); wrmsr(IA32_FEATURE_CONTROL, msr);
@ -93,9 +87,9 @@ static void configure_misc(void)
msr_t msr; msr_t msr;
msr = rdmsr(IA32_MISC_ENABLE); msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */ msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */ msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
wrmsr(IA32_MISC_ENABLE, msr); wrmsr(IA32_MISC_ENABLE, msr);
/* Disable Thermal interrupts */ /* Disable Thermal interrupts */