mb/google/brya/baseboard/nissa: Enable DPTF for Nissa variants

BUG=b:224884901
BRANCH=None
TEST=Build FW and test on Nivviks board

Change-Id: I3f5e8dd3d2ff517e27b0b08a0173f094bc6043bd
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>

src/mainboard/google/brya/variants/baseboard/nissa/devicetree.cb

@@ -22,6 +22,9 @@ chip soc/intel/alderlake
 	# S0ix enable
 	register "s0ix_enable" = "1"
 
+	# DPTF enable
+	register "dptf_enable" = "1"
+
 	# Enable CNVi BT
 	register "cnvi_bt_core" = "true"