diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c
index 0795990332..339e674a6e 100644
--- a/src/soc/intel/common/block/pmc/pmclib.c
+++ b/src/soc/intel/common/block/pmc/pmclib.c
@@ -416,18 +416,6 @@ int pmc_fill_power_state(struct chipset_power_state *ps)
 	ps->prev_sleep_state = pmc_prev_sleep_state(ps);
 	printk(BIOS_DEBUG, "prev_sleep_state %d\n", ps->prev_sleep_state);
 
-	/*
-	 * GPEs need to be disabled before enabling SMI. Otherwise, it could
-	 * lead to SMIs being triggered in coreboot preventing the progress of
-	 * normal boot-up. However, GPEs should not be disabled as part of
-	 * pmc_gpe_init which happens in bootblock. Otherwise,
-	 * pmc_fill_power_state would read GPE0_EN registers as all 0s thus
-	 * losing information about the wake source. Hence,
-	 * pmc_disable_all_gpe() is placed here after GPE0_EN registers are
-	 * saved in chipset_power_state.
-	 */
-	pmc_disable_all_gpe();
-
 	return ps->prev_sleep_state;
 }
 
diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c
index e8c52459a1..6059995493 100644
--- a/src/soc/intel/common/block/smm/smm.c
+++ b/src/soc/intel/common/block/smm/smm.c
@@ -45,6 +45,15 @@ void smm_southbridge_enable(uint16_t pm1_events)
 	pmc_enable_pm1(pm1_events);
 	pmc_disable_std_gpe(PME_B0_EN);
 
+	/*
+	 * GPEs need to be disabled before enabling SMI. Otherwise, it could
+	 * lead to SMIs being triggered in coreboot preventing the progress of
+	 * normal boot-up. This is done as late as possible so that
+	 * pmc_fill_power_state can read the correct state of GPE0_EN* registers
+	 * and not lose information about the wake source.
+	 */
+	pmc_disable_all_gpe();
+
 	/*
 	 * Enable SMI generation:
 	 *  - on APMC writes (io 0xb2)