soc/intel/{adl, cmn}: Allow config to select the OCP workaround

This patch introduces a config option for SoC code to choose
the applicable SoC workaround.

For now, we have introduced `SOC_INTEL_UFS_OCP_TIMER_DISABLE`
to apply UFS OCP timeout disable workaround.

At present ADL SoC only selects so, and in future MTL and others
should check with Intel prior selecting this kconfig.

It's the placeholder to add more workaround in required going forward.

BUG=none
TEST=Able to build and boot Google/Brya.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia2364d2de9725256dfa2269f2feb3d892c52086a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68309
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Subrata Banik 2022-10-12 14:24:41 +05:30 committed by Felix Held
parent bd12700be8
commit a00db94270
3 changed files with 18 additions and 0 deletions

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@ -425,6 +425,13 @@ config ACPI_ADL_IPU_ES_SUPPORT
help help
Enables ACPI entry to provide silicon type information to IPU kernel driver. Enables ACPI entry to provide silicon type information to IPU kernel driver.
config ALDERLAKE_ENABLE_SOC_WORKAROUND
bool
default y
select SOC_INTEL_UFS_OCP_TIMER_DISABLE
help
Selects the workarounds applicable for Alder Lake SoC.
choice choice
prompt "Multiprocessor (MP) Initialization configuration to use" prompt "Multiprocessor (MP) Initialization configuration to use"
default USE_FSP_MP_INIT default USE_FSP_MP_INIT

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@ -49,4 +49,11 @@ config SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID
help help
Defines hybrid CPU specific ACPI helper functions. Defines hybrid CPU specific ACPI helper functions.
config SOC_INTEL_UFS_OCP_TIMER_DISABLE
bool
help
OCP Timer need to be disabled in SCS UFS IOSF Bridge to
work around the Silicon Issue due to which LTR mechanism
doesn't work.
endif endif

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@ -67,8 +67,10 @@ Scope (\_SB.PCI0)
/* Set BIT[1:0] = 00b - Power State D0 */ /* Set BIT[1:0] = 00b - Power State D0 */
PSTA &= 0xFFFFFFFC PSTA &= 0xFFFFFFFC
#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
/* Disable OCP Timer in SCS UFS IOSF Bridge */ /* Disable OCP Timer in SCS UFS IOSF Bridge */
OCPD () OCPD ()
#endif
} }
Method (_PS3, 0, Serialized) Method (_PS3, 0, Serialized)
@ -79,7 +81,9 @@ Scope (\_SB.PCI0)
Method (_INI) Method (_INI)
{ {
#if CONFIG(SOC_INTEL_UFS_OCP_TIMER_DISABLE)
OCPD () OCPD ()
#endif
} }
} }
} }