rockchip/rk3399: update the ddr 200MHz frequency configuration
This patch updates the coreboot DDR Settings to match the configuration used by ARM-Trusted-Firmware. Change-Id: I34bc2950a9708ac89a5637bf682551e03d993fcc Signed-off-by: Caesar Wang <wxt@rock-chips.com> Reviewed-on: https://review.coreboot.org/20304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
This commit is contained in:
parent
d55f5ebe44
commit
a0199d8e1a
|
@ -636,7 +636,7 @@ void rkclk_configure_ddr(unsigned int hz)
|
|||
switch (hz) {
|
||||
case 200*MHz:
|
||||
dpll_cfg = (struct pll_div)
|
||||
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 6, .postdiv2 = 1};
|
||||
{.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 2};
|
||||
break;
|
||||
case 300*MHz:
|
||||
dpll_cfg = (struct pll_div)
|
||||
|
|
Loading…
Reference in New Issue