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soc/mediatek: a common implementation to register BL31 reset 

The implementations of register_reset_to_bl31() are the same for
MedaiTek platforms, so we extract them to soc/common/bl31.c.

BUG=None
TEST=build pass

Change-Id: I297ea2e18a6d7e92236cf415844b166523616bdf
Signed-off-by: Hung-Te Lin <hungte@chromium.org>
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67359
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
This commit is contained in:
Hung-Te Lin 2022-09-06 14:32:05 +08:00 committed by Felix Held
parent 70f30afa89
commit a01f8bc450
10 changed files with 49 additions and 60 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/mainboard/google/asurada/mainboard.c
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bl31.h>
#include <bootmode.h>
#include <console/console.h>
#include <delay.h>
@ -10,6 +9,7 @@
#include <edid.h>
#include <framebuffer_info.h>
#include <gpio.h>
#include <soc/bl31.h>
#include <soc/ddp.h>
#include <soc/dpm.h>
#include <soc/dsi.h>
@ -24,8 +24,6 @@
#include "gpio.h"
#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h>
#define MSDC0_BASE 0x11f60000
#define MSDC0_TOP_BASE 0x11f50000
@ -53,17 +51,6 @@
#define GPIO_AP_EDP_BKLTEN GPIO(KPROW1) /* 152 */
#define GPIO_BL_PWM_1V8 GPIO(DISP_PWM) /* 40 */
static void register_reset_to_bl31(void)
{
static struct bl_aux_param_gpio param_reset = {
.h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO },
.gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH },
};
param_reset.gpio.index = GPIO_RESET.id;
register_bl31_aux_param(&param_reset.h);
}
/* Override hs_da_trail for ANX7625 */
void mtk_dsi_override_phy_timing(struct mtk_phy_timing *timing)
{
@ -161,7 +148,8 @@ static void mainboard_init(struct device *dev)
configure_audio();
setup_usb_host();
register_reset_to_bl31();
if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
register_reset_to_bl31(GPIO_RESET.id, true);
if (dpm_init())
printk(BIOS_ERR, "dpm init fail, system can't do DVFS switch\n");

18
src/mainboard/google/cherry/mainboard.c
View File

@ -1,6 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bl31.h>
#include <boardid.h>
#include <bootmode.h>
#include <console/console.h>
@ -10,6 +9,7 @@
#include <edid.h>
#include <framebuffer_info.h>
#include <gpio.h>
#include <soc/bl31.h>
#include <soc/ddp.h>
#include <soc/dpm.h>
#include <soc/dptx.h>
@ -23,8 +23,6 @@
#include "gpio.h"
#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h>
/* GPIO to schematics names */
#define GPIO_AP_EDP_BKLTEN GPIO(DGI_D5)
#define GPIO_BL_PWM_1V8 GPIO(DISP_PWM0)
@ -57,17 +55,6 @@ bool mainboard_needs_pcie_init(void)
}
}
static void register_reset_to_bl31(void)
{
static struct bl_aux_param_gpio param_reset = {
.h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO },
.gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH },
};
param_reset.gpio.index = GPIO_RESET.id;
register_bl31_aux_param(&param_reset.h);
}
/* Set up backlight control pins as output pin and power-off by default */
static void configure_panel_backlight(void)
{
@ -160,7 +147,8 @@ static void mainboard_init(struct device *dev)
if (spm_init())
printk(BIOS_ERR, "spm init failed, system suspend may not work\n");
register_reset_to_bl31();
if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
register_reset_to_bl31(GPIO_RESET.id, true);
}
static void mainboard_enable(struct device *dev)

18
src/mainboard/google/corsola/mainboard.c
View File

@ -1,10 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bl31.h>
#include <bootmode.h>
#include <console/console.h>
#include <device/device.h>
#include <gpio.h>
#include <soc/bl31.h>
#include <soc/msdc.h>
#include <soc/spm.h>
#include <soc/usb.h>
@ -12,19 +12,6 @@
#include "display.h"
#include "gpio.h"
#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h>
static void register_reset_to_bl31(void)
{
static struct bl_aux_param_gpio param_reset = {
.h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO },
.gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH },
};
param_reset.gpio.index = GPIO_RESET.id;
register_bl31_aux_param(&param_reset.h);
}
static void configure_audio(void)
{
mtcmos_audio_power_on();
@ -54,7 +41,8 @@ static void mainboard_init(struct device *dev)
if (spm_init())
printk(BIOS_ERR, "spm init failed, system suspend may not work\n");
register_reset_to_bl31();
if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
register_reset_to_bl31(GPIO_RESET.id, true);
if (display_init_required()) {
if (configure_display() < 0)

18
src/mainboard/google/kukui/mainboard.c
View File

@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <assert.h>
#include <bl31.h>
#include <boardid.h>
#include <bootmode.h>
#include <cbfs.h>
@ -12,6 +11,7 @@
#include <edid.h>
#include <framebuffer_info.h>
#include <gpio.h>
#include <soc/bl31.h>
#include <soc/ddp.h>
#include <soc/dsi.h>
#include <soc/gpio.h>
@ -24,8 +24,6 @@
#include "gpio.h"
#include "panel.h"
#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h>
static void configure_emmc(void)
{
const gpio_t emmc_pin[] = {
@ -181,17 +179,6 @@ static bool configure_display(void)
return true;
}
static void register_reset_to_bl31(void)
{
static struct bl_aux_param_gpio param_reset = {
.h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO },
.gpio = { .polarity = ARM_TF_GPIO_LEVEL_HIGH },
};
param_reset.gpio.index = GPIO_RESET.id;
register_bl31_aux_param(&param_reset.h);
}
static void mainboard_init(struct device *dev)
{
if (display_init_required()) {
@ -211,7 +198,8 @@ static void mainboard_init(struct device *dev)
printk(BIOS_ERR,
"SPM initialization failed, suspend/resume may fail.\n");
register_reset_to_bl31();
if (CONFIG(ARM64_USE_ARM_TRUSTED_FIRMWARE))
register_reset_to_bl31(GPIO_RESET.id, true);
}
static void mainboard_enable(struct device *dev)

23
src/soc/mediatek/common/bl31.c Normal file
View File

@ -0,0 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <bl31.h>
#include <console/console.h>
#include <gpio.h>
#include <soc/bl31.h>
#include <arm-trusted-firmware/include/export/plat/mediatek/common/plat_params_exp.h>
void register_reset_to_bl31(int gpio_index, bool active_high)
{
static struct bl_aux_param_gpio param_reset = {
.h = { .type = BL_AUX_PARAM_MTK_RESET_GPIO },
};
if (active_high)
param_reset.gpio.polarity = ARM_TF_GPIO_LEVEL_HIGH;
else
param_reset.gpio.polarity = ARM_TF_GPIO_LEVEL_LOW;
param_reset.gpio.index = gpio_index;
register_bl31_aux_param(&param_reset.h);
}

10
src/soc/mediatek/common/include/soc/bl31.h Normal file
View File

@ -0,0 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
#ifndef _SOC_BL31_H_
#define _SOC_BL31_H_
#include <stdbool.h>
void register_reset_to_bl31(int gpio_index, bool active_high);
#endif /* _SOC_BL31_H_ */

1
src/soc/mediatek/mt8183/Makefile.inc
View File

@ -44,6 +44,7 @@ romstage-y += ../common/timer.c
romstage-y += ../common/uart.c
romstage-y += ../common/wdt.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
ramstage-y += emi.c
ramstage-y += ../common/auxadc.c
ramstage-y += ../common/ddp.c ddp.c

1
src/soc/mediatek/mt8186/Makefile.inc
View File

@ -27,6 +27,7 @@ romstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c
romstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c
ramstage-y += ../common/auxadc.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
ramstage-y += ../common/ddp.c ddp.c
ramstage-y += ../common/devapc.c devapc.c
ramstage-y += ../common/dfd.c

1
src/soc/mediatek/mt8192/Makefile.inc
View File

@ -32,6 +32,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
ramstage-y += apusys.c
ramstage-y += ../common/auxadc.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
ramstage-y += ../common/ddp.c ddp.c
ramstage-y += devapc.c
ramstage-y += ../common/dfd.c

1
src/soc/mediatek/mt8195/Makefile.inc
View File

@ -39,6 +39,7 @@ romstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c
ramstage-y += apusys.c
ramstage-y += apusys_devapc.c
ramstage-y += ../common/auxadc.c
ramstage-$(CONFIG_ARM64_USE_ARM_TRUSTED_FIRMWARE) += ../common/bl31.c
ramstage-y += ../common/early_init.c
ramstage-y += ../common/ddp.c ddp.c
ramstage-y += ../common/devapc.c devapc.c