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A couple of Poulsbo fixes: 

- Don't include cmc.bin to the build. It's required, but we don't ship it
- mptable's API changes a bit. Adapt.
- Fix ACPI for new iasl versions with improved code validation

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6199 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Patrick Georgi 2010-12-18 11:55:06 +00:00
parent be61a17351
commit a0360af0f1
3 changed files with 19 additions and 15 deletions
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2
src/mainboard/iwave/iWRainbowG6/mptable.c
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@ -29,7 +29,7 @@ void *smp_write_config_table(void *v)
int isa_bus; int isa_bus;
mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
mptable_init(mc, "IWRAINBOWG6", LAPIC_ADDR); mptable_init(mc, LAPIC_ADDR);
smp_write_processors(mc); smp_write_processors(mc);
mptable_write_buses(mc, NULL, &isa_bus); mptable_write_buses(mc, NULL, &isa_bus);

7
src/northbridge/intel/sch/acpi/hostbridge.asl
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@ -23,6 +23,9 @@
Name(_HID,EISAID("PNP0A08")) // PCIe Name(_HID,EISAID("PNP0A08")) // PCIe
Name(_CID,EISAID("PNP0A03")) // PCI Name(_CID,EISAID("PNP0A03")) // PCI
Name(_ADR, 0)
Name(_BBN, 0)
Device (MCHC) Device (MCHC)
{ {
Name(_ADR, 0x00000000) // 0:0.0 Name(_ADR, 0x00000000) // 0:0.0
@ -208,13 +211,13 @@ Method (_CRS, 0, Serialized)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite, Cacheable, ReadWrite,
0x00000000, 0x00000000, 0xfebfffff, 0x00000000, 0x00000000, 0x00000000, 0xfebfffff, 0x00000000,
0x00000000,,, PM01) 0xfec00000,,, PM01)
// TPM Area (0xfed40000-0xfed44fff) // TPM Area (0xfed40000-0xfed44fff)
DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed,
Cacheable, ReadWrite, Cacheable, ReadWrite,
0x00000000, 0xfed40000, 0xfed44fff, 0x00000000, 0x00000000, 0xfed40000, 0xfed44fff, 0x00000000,
0x00000000,,, TPMR) 0x00005000,,, TPMR)
}) })
// Find PCI resource area in MCRS // Find PCI resource area in MCRS

9
src/southbridge/intel/sch/Makefile.inc
View File

@ -35,7 +35,8 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
romstage-$(CONFIG_USBDEBUG) += usb_debug.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c
cbfs-files-y += cmc.bin # We don't ship that, but booting without it is bound to fail
cmc.bin-name := cmc.bin #cbfs-files-y += cmc.bin
cmc.bin-type := 0xaa #cmc.bin-name := cmc.bin
cmc.bin-position := 0xfffd0000 #cmc.bin-type := 0xaa
#cmc.bin-position := 0xfffd0000