soc/intel/{cml, whl}: Add option to skip HECI disable in SMM

This patch provides an additional option to skip HECI function
disabling using SMM mode for WHL and CML platform, where FSP has
dedicated UPD to make HECI function disable.

User to select HECI_DISABLE_USING_SMM if FSP doesn't provided dedicated
UPD.

Right now CNL and ICL platform will use HECI_DISABLE_USING_SMM kconfig
to make HECI disable and WHL/CML has to rely on FSP to make HECI
disable.

Change-Id: If3b064f3c32877235916f966a01beb525156d188
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33193
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/soc/intel/cannonlake/Kconfig

@@ -107,6 +107,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDK_2017_BINDING
 	select DISPLAY_FSP_VERSION_INFO
 	select FSP_T_XIP if FSP_CAR
+	select HECI_DISABLE_USING_SMM if !SOC_INTEL_COFFEELAKE && !SOC_INTEL_WHISKEYLAKE && !SOC_INTEL_COMETLAKE
 
 config DCACHE_RAM_BASE
 	default 0xfef00000

src/soc/intel/cannonlake/smihandler.c

@@ -88,7 +88,7 @@ void smihandler_soc_at_finalize(void)
 
 	config = dev->chip_info;
 
-	if (config->HeciEnabled == 0)
+	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
 		pch_disable_heci();
 }
 

src/soc/intel/common/block/smm/Kconfig

@@ -23,3 +23,11 @@ config SOC_INTEL_COMMON_BLOCK_SMM_S5_DELAY_MS
 	  Time in milliseconds that SLP_SMI for S5 waits for before
 	  enabling sleep. This is required to avoid any race between
 	  SLP_SMI and PWRBTN SMI.
+
+config HECI_DISABLE_USING_SMM
+	bool
+	depends on SOC_INTEL_COMMON_BLOCK_SMM
+	default n
+	help
+	  HECI disable using SMM. Select this option to make HECI disable
+	  using SMM mode, independent of dedicated UPD to perform HECI disable.

src/soc/intel/icelake/Kconfig

@@ -62,6 +62,7 @@ config CPU_SPECIFIC_OPTIONS
 	select UDELAY_TSC
 	select UDK_2017_BINDING
 	select DISPLAY_FSP_VERSION_INFO
+	select HECI_DISABLE_USING_SMM
 
 config DCACHE_RAM_BASE
 	default 0xfef00000

src/soc/intel/icelake/smihandler.c

@@ -86,7 +86,7 @@ void smihandler_soc_at_finalize(void)
 
 	config = dev->chip_info;
 
-	if (config->HeciEnabled == 0)
+	if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
 		pch_disable_heci();
 }