mb/supermicro/x11: Make use of chipset devicetree
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
Michael Niewöhner
parent
7713a2f295
commit
a03999be25
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@ -28,56 +28,12 @@ chip soc/intel/skylake
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device cpu_cluster 0 on end
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device domain 0 on
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device pci 00.0 on end # Host Bridge
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device pci 01.0 off end # CPU PCIe Port 10 (x16)
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device pci 01.1 off end # CPU PCIe Port 11 (x8)
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device pci 01.2 off end # CPU PCIe Port 12 (x4)
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device pci 02.0 off end # Integrated Graphics Device (IGD)
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device pci 04.0 on end # SA thermal subsystem
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device pci 05.0 off end # Imaging Unit
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device pci 08.0 off end # Gaussion Mixture Model (GMM)
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device pci 13.0 off end # Integrated Sensor Hub
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device pci 14.0 on end # USB xHCI
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device pci 14.1 off end # USB xDCI (OTG)
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device pci 14.2 on end # Thermal Subsystem
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device pci 15.0 off end # I2C #0
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device pci 15.1 off end # I2C #1
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device pci 15.2 off end # I2C #2
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device pci 15.3 off end # I2C #3
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT Redirection
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device pci 16.4 off end # Management Engine Interface 3
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device pci 17.0 on end # SATA
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device pci 19.0 off end # UART #2
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device pci 19.1 off end # I2C #5
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device pci 19.2 off end # I2C #4
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device pci 1b.0 off end # PCH PCIe Port 17
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device pci 1b.1 off end # PCH PCIe Port 18
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device pci 1b.2 off end # PCH PCIe Port 19
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device pci 1b.3 off end # PCH PCIe Port 20
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device pci 1c.0 off end # PCH PCIe Port 1
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device pci 1c.1 off end # PCH PCIe Port 2
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device pci 1c.2 off end # PCH PCIe Port 3
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device pci 1c.3 off end # PCH PCIe Port 4
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device pci 1c.4 off end # PCH PCIe Port 5
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device pci 1c.5 off end # PCH PCIe Port 6
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device pci 1c.6 off end # PCH PCIe Port 7
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device pci 1c.7 off end # PCH PCIe Port 8
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device pci 1d.0 off end # PCH PCIe Port 9
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device pci 1d.1 off end # PCH PCIe Port 10
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device pci 1d.2 off end # PCH PCIe Port 11
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device pci 1d.3 off end # PCH PCIe Port 12
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device pci 1d.4 off end # PCH PCIe Port 13
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device pci 1d.5 off end # PCH PCIe Port 14
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device pci 1d.6 off end # PCH PCIe Port 15
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device pci 1d.7 off end # PCH PCIe Port 16
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device pci 1e.0 off end # UART #0
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device pci 1e.1 off end # UART #1
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device pci 1e.2 off end # SPI #0
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device pci 1e.6 off end # SDXC
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device pci 1f.0 on # LPC Interface
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device ref sa_thermal on end
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device ref south_xhci on end
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device ref thermal on end
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device ref heci1 on end
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device ref sata on end
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device ref lpc_espi on
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chip superio/common
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device pnp 2e.0 on end
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end
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@ -85,12 +41,7 @@ chip soc/intel/skylake
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device pnp 0c31.0 on end
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end
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end
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device pci 1f.1 on end # P2SB
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device pci 1f.2 on end # Power Management Controller
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device pci 1f.3 off end # Intel HDA
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device pci 1f.4 on end # SMBus
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device pci 1f.5 on end # SPI Controller
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device pci 1f.6 off end # GbE
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device pci 1f.7 off end # Intel Trace Hub
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device ref smbus on end
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device ref fast_spi on end
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end
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end
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@ -41,44 +41,47 @@ chip soc/intel/skylake
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}"
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device domain 0 on
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device pci 01.0 on
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device ref peg0 on
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# Slot JPCIE3
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"
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end # CPU PCIE Slot (JPCIE3)
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device pci 01.1 on # CPU PCIE Slot (JPCIE2)
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end
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device ref peg1 on
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# Slot JPCIE2
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth8X"
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end
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device pci 02.0 on end # Integrated Graphics Device (No Output)
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device pci 1c.0 on # PCI Express Port 1
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device ref igpu on end
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device ref pcie_rp1 on
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register "PcieRpEnable[0]" = "1"
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device pci 00.0 on end # GbE
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end
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device pci 1c.1 on # PCI Express Port 2
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device ref pcie_rp2 on
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register "PcieRpEnable[1]" = "1"
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device pci 00.0 on end # GbE
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end
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device pci 1c.2 on # PCI Express Port 3 only on -LN4F
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device ref pcie_rp3 on
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register "PcieRpEnable[2]" = "1"
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device pci 00.0 on end # GbE
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end
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device pci 1c.3 on # PCI Express Port 4 only on -LN4F
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device ref pcie_rp4 on
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register "PcieRpEnable[3]" = "1"
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device pci 00.0 on end # GbE
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end
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device pci 1c.4 on # PCI Express Port 5
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device ref pcie_rp5 on
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register "PcieRpEnable[4]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth2X"
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end
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device pci 1c.6 on # PCI Express Port 7
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device ref pcie_rp7 on
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register "PcieRpEnable[6]" = "1"
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device pci 00.0 on # Aspeed PCI Bridge
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device pci 00.0 on end # Aspeed 2400 VGA
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end
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end
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device pci 1d.0 on # PCI Express Port 9 (Slot JPCIE1)
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device ref pcie_rp9 on
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# Slot JPCIE1
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register "PcieRpEnable[8]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
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end
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device pci 1f.0 on # LPC Interface
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device ref lpc_espi on
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chip drivers/ipmi
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# On cold boot it takes a while for the BMC to start the IPMI service
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register "wait_for_bmc" = "1"
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@ -40,30 +40,32 @@ chip soc/intel/skylake
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}"
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device domain 0 on
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device pci 01.0 on end # unused
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device pci 01.1 on # PCIE Slot (JPCIE1)
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device ref peg0 on end # unused
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device ref peg1 on
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# Slot JPCIE1
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register "PcieRpEnable[0]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X"
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end
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device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1)
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device ref pcie_rp1 on
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# Slot JPCIE1
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register "PcieRpEnable[2]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X"
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end
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device pci 1c.2 on # PCI Express Port 3
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device ref pcie_rp3 on
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device pci 00.0 on # Aspeed PCI Bridge
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device pci 00.0 on end # Aspeed 2400 VGA
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end
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end
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device pci 1c.4 on # PCI Express Port 5
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device ref pcie_rp5 on
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register "PcieRpEnable[4]" = "1"
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device pci 00.0 on end # 10GbE
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device pci 00.1 on end # 10GbE
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end
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device pci 1d.0 on # PCI Express Port 9
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device ref pcie_rp9 on
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register "PcieRpEnable[8]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
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end
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device pci 1f.0 on # LPC Interface
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device ref lpc_espi on
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chip drivers/ipmi
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use pch_gpio as gpio_dev
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register "post_complete_gpio" = "GPP_B20"
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@ -36,25 +36,29 @@ chip soc/intel/skylake
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device domain 0 on
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subsystemid 0x15d9 0x0896 inherit
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device pci 01.0 on # CPU PCIe Port (x16) / PCIe Slot 6 (JPCIE6)
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device ref peg0 on
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# Slot JPCIE6
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT6 PCI-E 3.0 X8(IN X16)" "SlotDataBusWidth8X"
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end
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device pci 01.1 on # CPU PCIe Port (x8) / PCIe Slot 7 (JPCIE7)
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device ref peg1 on
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# Slot JPCIE7
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X"
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end
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device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4)
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device ref pcie_rp1 on
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# Slot JPCIE4
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register "PcieRpEnable[0]" = "1"
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register "PcieRpLtrEnable[0]" = "1"
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register "PcieRpAdvancedErrorReporting[0]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
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end
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device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5)
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device ref pcie_rp5 on
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# Slot JPCIE5
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register "PcieRpEnable[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
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end
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device pci 1d.0 on # PCH PCIe Port 9
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device ref pcie_rp9 on
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register "PcieRpEnable[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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register "PcieRpAdvancedErrorReporting[8]" = "1"
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@ -62,7 +66,7 @@ chip soc/intel/skylake
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subsystemid 0x15d9 0x1533
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end
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end
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device pci 1d.1 on # PCH PCIe Port 10
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device ref pcie_rp10 on
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register "PcieRpEnable[9]" = "1"
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register "PcieRpLtrEnable[9]" = "1"
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register "PcieRpAdvancedErrorReporting[9]" = "1"
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@ -70,7 +74,7 @@ chip soc/intel/skylake
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subsystemid 0x15d9 0x1533
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end
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end
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device pci 1d.2 on # PCH PCIe Port 11
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device ref pcie_rp11 on
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register "PcieRpEnable[10]" = "1"
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register "PcieRpLtrEnable[10]" = "1"
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register "PcieRpAdvancedErrorReporting[10]" = "1"
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@ -78,7 +82,7 @@ chip soc/intel/skylake
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device pci 00.0 on end # Aspeed 2400 VGA
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end
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end
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device pci 1f.0 on # LPC Interface
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device ref lpc_espi on
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chip drivers/ipmi
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use pch_gpio as gpio_dev
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register "bmc_jumper_gpio" = "GPP_D22" # JPB1
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@ -42,32 +42,34 @@ chip soc/intel/skylake
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}"
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device domain 0 on
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device pci 01.0 on
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device ref peg0 on
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# Slot JSXB1B
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smbios_slot_desc "SlotTypePciExpressGen3X16" "SlotLengthLong" "CPU SLOT1 PCI-E 3.0 X16" "SlotDataBusWidth16X"
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end # CPU PCIE Slot JSXB1B
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device pci 1c.0 on # PCI Express Port 1
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end
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device ref pcie_rp1 on
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register "PcieRpEnable[0]" = "1"
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device pci 00.0 on end # GbE
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end
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device pci 1c.1 on # PCI Express Port 2
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device ref pcie_rp2 on
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register "PcieRpEnable[1]" = "1"
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device pci 00.0 on end # GbE
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end
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device pci 1c.4 on # PCI Express Port 5
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device ref pcie_rp5 on
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register "PcieRpEnable[4]" = "1"
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smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X"
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end
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device pci 1d.0 on # PCI Express Port 9 (Slot JSXB2)
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device ref pcie_rp9 on
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# Slot JSXB2
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register "PcieRpEnable[8]" = "1"
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smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthShort" "PCH SLOT2 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X"
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end
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device pci 1d.4 on # PCI Express Port 13
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device ref pcie_rp13 on
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register "PcieRpEnable[12]" = "1"
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device pci 00.0 on # Aspeed PCI Bridge
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device pci 00.0 on end # Aspeed 2400 VGA
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end
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end
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device pci 1f.0 on # LPC Interface
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device ref lpc_espi on
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chip drivers/ipmi
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# On cold boot it takes a while for the BMC to start the IPMI service
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register "wait_for_bmc" = "1"
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