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mb/google/hatch/var/ambassador: configure FSP option PcieRpSlotImplemented 

Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.

Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Matt Ziegelbaum 2020-11-17 17:20:04 -05:00 committed by Furquan Shaikh
parent 552133e161
commit a04072c917
1 changed files with 4 additions and 1 deletions
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5
src/mainboard/google/hatch/variants/ambassador/overridetree.cb
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@ -402,8 +402,11 @@ chip soc/intel/cannonlake
register "device_index" = "0" register "device_index" = "0"
device pci 00.0 on end device pci 00.0 on end
end end
register "PcieRpSlotImplemented[6]" = "1"
end # RTL8111H Ethernet NIC end # RTL8111H Ethernet NIC
device pci 1d.2 on end # PCI Express Port 11 (X2 NVMe) device pci 1d.2 on # PCI Express Port 11 (X2 NVMe)
register "PcieRpSlotImplemented[10]" = "1"
end
device pci 1e.3 off end # GSPI #1 device pci 1e.3 off end # GSPI #1
end end