vendorcode/intel/fsp/rangeley: remove extra file
This is an extra file that is included in the Intel GSP release. It's got a coreboot header on it, isn't used, and looks very platform specific. I'm not sure where it belongs, but it doesn't belong in vendorcode. I've sent the contacts at Intel an email letting them know that this file should probably be removed from their FSP release and is getting removed here. Change-Id: I5ac6649235846ce5716bb180af29a5e422f4cce3 Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5809 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
This commit is contained in:
Martin Roth
Martin Roth
parent
e9e99e976e
commit
a0427cb844
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@ -1,521 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007-2008 coresystems GmbH
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* Copyright (C) 2013, Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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// __PRE_RAM__ means: use "unsigned" for device, not a struct.
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#include <arch/romcc_io.h>
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#include <device/pci_def.h>
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#include <device/pnp_def.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/stack.h>
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#include <pc80/mc146818rtc.h>
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#include <console/console.h>
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#include <spi.h>
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#include <spi_flash.h>
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#include <cbmem.h>
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#include <ip_checksum.h>
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#include "fsptypes.h"
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#include "fspfv.h"
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#include "fspffs.h"
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#include "fsphob.h"
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#include "fspvpd.h"
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#include "fspapi.h"
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#include "fspplatform.h"
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#include "fspinfoheader.h"
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#include "fspbootmode.h"
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#include "northbridge/intel/rangeley/northbridge.h"
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void find_fsp_header(void);
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void early_init(FSP_INFO_HEADER *fsp_info);
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void FspNotifyPhase(uint32_t Phase);
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void UpdateFspUpdConfigs (
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UPD_DATA_REGION *FspUpdRgn
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);
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//
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// Spd Data table for Memory Down
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//
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#ifdef __PRE_RAM__
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#if CONFIG_MEMORY_DOWN_ENABLE
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/*
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* MEM_DOWN_DIMM_CONFIG
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* MemoryDownDimmPopulation - 0: Empty 1: Populated.
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* MemoryDownDimmSpdData - structure MEM_DOWN_DIMM_SPD_DATA for spd data.
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*/
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/* Apacer 2GB PC3-12800 DDR3-1600MHz ECC Unbuffered CL11 240-Pin DIMM Single Rank Memory Module Mfr P/N 78.A1GG3.AF20C */
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static const MEM_DOWN_DIMM_CONFIG OemMemoryDownDimmConfig = {
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0x01, // MemoryDownDimmPopulation
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{ // MemoryDownDimmSpdData
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0xB, //Byte 2 Dram Device Type
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0x2, //Byte 3 Module type (3:0)
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0x3, //Byte 4 Density and Banks
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0x19, //Byte 5 Addressing
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0x2, //Byte 6 Nominal Voltage, VDD
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0x1, //Byte 7 Module Organization
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0xB, //Byte 8 Memory Bus Width
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0x1, //Byte 10 Medium Timebase (MTB) Dividend
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0x8, //Byte 11 Medium Timebase (MTB) Divisor
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0xA, //Byte 12 Minimum cycle time (tCKmin)
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0xFC, //Byte 14 CAS latency supported, low byte
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0, //Byte 15 CAS latency supported, high byte
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0x69, //Byte 16 Minimum CAS latency time (tAA)
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0x78, //Byte 17 Minimum write recovery time (tWR)
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0x69, //Byte 18 Minimum RAS to CAS time (tRCD)
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0x30, //Byte 19 Minimum RA to RA time (tRRD)
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0x69, //Byte 20 Minimum precharge time (tRP)
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0x11, //Byte 21 Upper nibbles for tRAS (7:4), tRC (3:0)
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0x18, //Byte 22 Minimum active to precharge (tRAS)
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0x81, //Byte 23 Minimum active to active/refresh (tRC)
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0, //Byte 24 Minimum refresh recovery (tRFC), low byte
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0x5, //Byte 25 Minimum refresh recovery (tRFC), high byte
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0x3C, //Byte 26 Minimum internal wr to rd cmd (tWTR)
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0x3C, //Byte 27 Minimum internal rd to pc cmd (tRTP)
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0, //Byte 28 Upper Nibble for tFAW
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0xF0, //Byte 29 Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte
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0x80, //Byte 32
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0, //Byte 33
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0, //Byte 34
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0, //Byte 35
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0, //Byte 41
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0x3, //Byte 62
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0, //Byte 63
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0x1, //Byte 117
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0x7A, //Byte 118
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0, //Byte 119
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0x13, //Byte 120
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0x15, //Byte 121
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0x2, //Byte 122
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0x1, //Byte 123
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0x31, //Byte 124
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0x52, //Byte 125
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0, //Byte 148
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0, //Byte 149
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}
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};
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/* Dummy structure */
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static const MEM_DOWN_DIMM_CONFIG DummyMemoryDownDimmConfig = {
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0x00, // MemoryDownDimmPopulation
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{ // MemoryDownDimmSpdData
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0, //Byte 2 Dram Device Type
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0, //Byte 3 Module type (3:0)
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0, //Byte 4 Density and Banks
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0, //Byte 5 Addressing
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0, //Byte 6 Nominal Voltage, VDD
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0, //Byte 7 Module Organization
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0, //Byte 8 Memory Bus Width
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0, //Byte 10 Medium Timebase (MTB) Dividend
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0, //Byte 11 Medium Timebase (MTB) Divisor
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0, //Byte 12 Minimum cycle time (tCKmin)
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0, //Byte 14 CAS latency supported, low byte
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0, //Byte 15 CAS latency supported, high byte
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0, //Byte 16 Minimum CAS latency time (tAA)
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0, //Byte 17 Minimum write recovery time (tWR)
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0, //Byte 18 Minimum RAS to CAS time (tRCD)
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0, //Byte 19 Minimum RA to RA time (tRRD)
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0, //Byte 20 Minimum precharge time (tRP)
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0, //Byte 21 Upper nibbles for tRAS (7:4), tRC (3:0)
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0, //Byte 22 Minimum active to precharge (tRAS)
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0, //Byte 23 Minimum active to active/refresh (tRC)
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0, //Byte 24 Minimum refresh recovery (tRFC), low byte
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0, //Byte 25 Minimum refresh recovery (tRFC), high byte
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0, //Byte 26 Minimum internal wr to rd cmd (tWTR)
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0, //Byte 27 Minimum internal rd to pc cmd (tRTP)
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0, //Byte 28 Upper Nibble for tFAW
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0, //Byte 29 Minimum Four Activate Window Delay Time (tFAWmin), Least Significant Byte
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0, //Byte 32
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0, //Byte 33
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0, //Byte 34
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0, //Byte 35
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0, //Byte 41
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0, //Byte 62
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0, //Byte 63
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0, //Byte 117
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0, //Byte 118
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0, //Byte 119
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0, //Byte 120
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0, //Byte 121
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0, //Byte 122
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0, //Byte 123
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0, //Byte 124
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0, //Byte 125
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0, //Byte 148
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0, //Byte 149
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}
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};
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#endif
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#endif
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//
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// FSP_INFO_HEADER GUID
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//
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#define FSP_INFO_HEADER_GUID \
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{ \
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0x912740BE, 0x2284, 0x4734, {0xB9, 0x71, 0x84, 0xB0, 0x27, 0x35, 0x3F, 0x0C} \
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}
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//
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// FSP_NON_VOLATILE_STORAGE_HOB_GUID
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//
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#define FSP_NON_VOLATILE_STORAGE_HOB_GUID \
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{ \
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0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, 0x27, 0xb, 0x7b, 0xa9, 0xe4, 0xb0} \
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}
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static EFI_GUID gFspInfoHeaderGuid = FSP_INFO_HEADER_GUID;
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#ifdef __PRE_RAM__
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static EFI_GUID gEfiMemoryConfigDataGuid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
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#endif
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/*
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* Compares two GUIDs.
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* Input:
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* Guid1 a 128 bit GUID.
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* Guid2 a 128 bit GUID.
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* Return:
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* TRUE Guid1 and Guid2 are identical.
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* FALSE Guid1 and Guid2 are not identical.
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*/
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#define CompareGuid(Guid1, Guid2) ( \
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(Guid1.Data1 == Guid2.Data1) && \
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(Guid1.Data2 == Guid2.Data2) && \
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(Guid1.Data3 == Guid2.Data3) && \
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(Guid1.Data4[0] == Guid2.Data4[0]) && \
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(Guid1.Data4[1] == Guid2.Data4[1]) && \
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(Guid1.Data4[2] == Guid2.Data4[2]) && \
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(Guid1.Data4[3] == Guid2.Data4[3]) && \
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(Guid1.Data4[4] == Guid2.Data4[4]) && \
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(Guid1.Data4[5] == Guid2.Data4[5]) && \
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(Guid1.Data4[6] == Guid2.Data4[6]) && \
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(Guid1.Data4[7] == Guid2.Data4[7]) \
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)
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/*
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* Compares two GUIDs.
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* Input:
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* Guid1 A pointer to a 128 bit GUID.
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* Guid2 A pointer to a 128 bit GUID.
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* Return:
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* TRUE Guid1 and Guid2 are identical.
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* FALSE Guid1 and Guid2 are not identical.
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*/
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#define CompareGuidPtr(Guid1, Guid2) ( \
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(((UINT32 *) Guid1)[0] == ((UINT32 *) Guid2)[0]) && \
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(((UINT32 *) Guid1)[1] == ((UINT32 *) Guid2)[1]) && \
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(((UINT32 *) Guid1)[2] == ((UINT32 *) Guid2)[2]) && \
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(((UINT32 *) Guid1)[3] == ((UINT32 *) Guid2)[3]) \
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)
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/*
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* Platform configuration pointer/structure here.
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*/
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#ifdef __PRE_RAM__
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static void ContinuationFunc (EFI_STATUS Status, void *HobListPtr)
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{
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/* Should add the necessary code here! */
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EFI_HOB_GUID_TYPE *GuidHob;
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/*
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* DO NOT know why the following code always fail to build.
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*
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* GuidHob = GetNextGuidHob (&gEfiMemoryConfigDataGuid, HobListPtr);
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*
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* The error message as below,
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*
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* .data is non-zero size in romstage which is not allowed -- global variable?
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*
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* OR,
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*
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* .bss is non-zero size in romstage which is not allowed -- global variable?
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*
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* It's replaced with the following code.
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*/
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/* Get the Memory Configure Data HOB */
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EFI_PEI_HOB_POINTERS mGuidHob;
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mGuidHob.Raw = (UINT8 *) HobListPtr;
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while ((mGuidHob.Raw = GetNextHob (EFI_HOB_TYPE_GUID_EXTENSION, mGuidHob.Raw)) != NULL) {
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if (CompareGuid(gEfiMemoryConfigDataGuid, mGuidHob.Guid->Name)) {
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break;
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}
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mGuidHob.Raw = GET_NEXT_HOB (mGuidHob);
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}
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GuidHob = (EFI_HOB_GUID_TYPE *) mGuidHob.Raw;
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if (GuidHob == NULL) {
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/* Avoid store Hob to CBMEM if NVRAM Hob not exist */
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printk(BIOS_DEBUG, "FSP NVRAM Hob NOT found.\n");
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} else {
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/* Get Guid Hob size and Guid Hob Data pointer */
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void *GuidHobData;
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uint32_t GuidHobSize;
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GuidHobData = (VOID *)(*(UINT8 **)&(mGuidHob.Raw) + sizeof (EFI_HOB_GUID_TYPE));
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GuidHobSize = (uint32_t) ((((EFI_HOB_GUID_TYPE *)(mGuidHob.Raw))->Header.HobLength) - sizeof(EFI_HOB_GUID_TYPE));
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/* DEBUG INFO */
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printk(BIOS_DEBUG, "FSP NVRAM Hob at 0x%x (size = 0x%x).\n", (uint32_t)GuidHobData, (uint32_t)GuidHobSize);
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#if CONFIG_EARLY_CBMEM_INIT
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struct mrc_data_container *mrcdata;
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int output_len = ALIGN(GuidHobSize, 16);
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/* Save the MRC S3/Fastboot/ADR restore data to cbmem */
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cbmem_initialize();
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mrcdata = cbmem_add
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(CBMEM_ID_MRCDATA,
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output_len + sizeof(struct mrc_data_container));
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printk(BIOS_DEBUG, "Relocate MRC DATA from %p to %p (%u bytes)\n",
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(void *)GuidHobData, mrcdata, output_len);
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mrcdata->mrc_signature = MRC_DATA_SIGNATURE;
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mrcdata->mrc_data_size = output_len;
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mrcdata->reserved = 0;
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memcpy(mrcdata->mrc_data, (void *)GuidHobData,
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GuidHobSize);
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/* Zero the unused space in aligned buffer. */
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if (output_len > GuidHobSize)
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memset(mrcdata->mrc_data + GuidHobSize, 0,
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output_len - GuidHobSize);
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mrcdata->mrc_checksum = compute_ip_checksum(mrcdata->mrc_data,
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mrcdata->mrc_data_size);
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#endif
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}
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/* Rangeley early init */
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rangeley_early_initialization();
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/* Notify FSP for PostPciEnumeration */
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FspNotifyPhase (EnumInitPhaseAfterPciEnumeration);
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/* Return to coreboot boot process. */
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__asm__ __volatile__ (
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"jmp fsp_init_done\n\t"
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);
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}
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/** C Based Basic Initialization
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*
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* Platform configuration with Temp Stack starts here.
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*
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*/
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void early_init (FSP_INFO_HEADER *fsp_info)
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{
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FSP_FSP_INIT FspInitApi;
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FSP_INIT_PARAMS FspInitParams;
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FSP_INIT_RT_BUFFER FspRtBuffer;
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VPD_DATA_REGION *FspVpdRgn;
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UPD_DATA_REGION FspUpdRgn;
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struct mrc_data_container *mrc_cache;
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memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
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FspRtBuffer.Common.StackTop = (uint32_t *) ROMSTAGE_STACK;
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FspRtBuffer.Common.UpdDataRgnPtr = (UPD_DATA_REGION *)&FspUpdRgn;
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/* find_current_mrc_cache */
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if (((mrc_cache = find_current_mrc_cache()) == NULL) || (mrc_cache->mrc_data_size == -1UL)) {
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printk(BIOS_DEBUG, "MRC cache not present.\n");
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FspInitParams.NvsBufferPtr = (void *) NULL;
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FspRtBuffer.Common.BootMode = BOOT_WITH_FULL_CONFIGURATION;
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} else {
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printk(BIOS_DEBUG, "MRC cache present at %x.\n", (uint32_t)mrc_cache);
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FspInitParams.NvsBufferPtr = (void *) (EFI_HOB_GUID_TYPE *) mrc_cache->mrc_data;
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FspRtBuffer.Common.BootMode = BOOT_WITH_FULL_CONFIGURATION;
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}
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/* Get VPD region start */
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FspVpdRgn = (VPD_DATA_REGION *)(fsp_info->ImageBase + fsp_info->CfgRegionOffset);
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/* Verifify the VPD data region is valid */
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ASSERT((FspVpdRgn->PcdImageRevision == VPD_IMAGE_REV) && (FspVpdRgn->PcdVpdRegionSign == VPD_IMAGE_ID));
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/* Copy default data from Flash */
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memcpy ((void*)&FspUpdRgn, (void *)(fsp_info->ImageBase + FspVpdRgn->PcdUpdRegionOffset), sizeof(UPD_DATA_REGION));
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/* Verifify the UPD data region is valid */
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ASSERT(FspUpdRgn.PcdRegionTerminator == 0x55AA);
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/* Override any UPD setting if required */
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UpdateFspUpdConfigs (&FspUpdRgn);
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#if CONFIG_MEMORY_DOWN_ENABLE
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/*
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* Setup platform specific structure
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*/
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/* Channel0/Dimm0, DIMM populated */
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FspRtBuffer.Platform.MemDownDimmConfig[0][0] = (MEM_DOWN_DIMM_CONFIG *)&OemMemoryDownDimmConfig;
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/* Channel0/Dimm1, not populated */
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FspRtBuffer.Platform.MemDownDimmConfig[0][1] = (MEM_DOWN_DIMM_CONFIG *)&DummyMemoryDownDimmConfig;
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/* Channel1/Dimm0, DIMM populated */
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FspRtBuffer.Platform.MemDownDimmConfig[1][0] = (MEM_DOWN_DIMM_CONFIG *)&OemMemoryDownDimmConfig;
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/* Channel1/Dimm1, not populated */
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FspRtBuffer.Platform.MemDownDimmConfig[1][1] = (MEM_DOWN_DIMM_CONFIG *)&DummyMemoryDownDimmConfig;
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#endif
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FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer;
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FspInitParams.ContinuationFunc = (CONTINUATION_PROC)ContinuationFunc;
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FspInitApi = (FSP_FSP_INIT)(fsp_info->ImageBase + fsp_info->FspInitEntry);
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FspInitApi(&FspInitParams);
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/* Should never return. Control will continue from ContinuationFunc */
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while (1);
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}
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#endif
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/** C Based Basic Initialization
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*
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* Find FSP header
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*
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*/
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void __attribute__((optimize("O0"))) find_fsp_header ()
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{
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volatile register UINT8 *ptr asm ("eax");
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#ifdef __PRE_RAM__
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__asm__ __volatile__ (
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".global find_fsp_entry\n\t"
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"find_fsp_entry:\n\t"
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);
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#endif
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//
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// Start at the FSP / FV Header base
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//
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||||
ptr = (UINT8 *)CONFIG_FSP_BIN_BASE;
|
||||
|
||||
//
|
||||
// Validate FV signature _FVH
|
||||
//
|
||||
if (((EFI_FIRMWARE_VOLUME_HEADER *)ptr)-> Signature != EFI_FVH_SIGNATURE) {
|
||||
ptr = 0;
|
||||
goto NotFound;
|
||||
}
|
||||
|
||||
//
|
||||
// Add the Ext Header size to the Ext Header base to go to the end of FV
|
||||
// header
|
||||
//
|
||||
ptr += ((EFI_FIRMWARE_VOLUME_HEADER *)ptr)->ExtHeaderOffset;
|
||||
ptr += ((EFI_FIRMWARE_VOLUME_EXT_HEADER *)ptr)->ExtHeaderSize;
|
||||
|
||||
//
|
||||
// Align the end of FV header address to 8 bytes
|
||||
//
|
||||
ptr = (UINT8 *)(((uint32_t)ptr + 7) & 0xFFFFFFF8);
|
||||
|
||||
//
|
||||
// Now ptr is pointing to thr FFS Header. Verify if the GUID
|
||||
// matches the FSP_INFO_HEADER GUID
|
||||
//
|
||||
if (!CompareGuid(((EFI_GUID) (((EFI_FFS_FILE_HEADER *)ptr)->Name)), ((EFI_GUID) gFspInfoHeaderGuid))) {
|
||||
ptr = 0;
|
||||
goto NotFound;
|
||||
}
|
||||
|
||||
//
|
||||
// Add the FFS Header size to the base to find the Raw section Header
|
||||
//
|
||||
ptr += sizeof(EFI_FFS_FILE_HEADER);
|
||||
if (((EFI_RAW_SECTION *)ptr)->Type != EFI_SECTION_RAW) {
|
||||
ptr = 0;
|
||||
goto NotFound;
|
||||
}
|
||||
|
||||
//
|
||||
// Add the Raw Header size to the base to find the FSP INFO Header
|
||||
//
|
||||
ptr += sizeof(EFI_RAW_SECTION);
|
||||
|
||||
NotFound:
|
||||
__asm__ __volatile__ ("ret");
|
||||
}
|
||||
|
||||
/** C Based Basic Initialization
|
||||
*
|
||||
* Notify Phase for different stage.
|
||||
*
|
||||
*/
|
||||
void FspNotifyPhase (uint32_t Phase)
|
||||
{
|
||||
FSP_NOTFY_PHASE NotifyPhaseProc;
|
||||
NOTIFY_PHASE_PARAMS NotifyPhaseParams;
|
||||
FSP_INFO_HEADER *fsp_info_header;
|
||||
EFI_STATUS Status;
|
||||
|
||||
__asm__ __volatile__ (
|
||||
"call find_fsp_header \n\t" /* Call FSP Notify API */
|
||||
"movl %%eax, %0\n\t"
|
||||
: "=m"(fsp_info_header) ::
|
||||
);
|
||||
|
||||
/* call FSP PEI to Notify PostPciEnumeration */
|
||||
NotifyPhaseProc = (FSP_NOTFY_PHASE)(fsp_info_header->ImageBase + fsp_info_header->NotifyPhaseEntry);
|
||||
NotifyPhaseParams.Phase = Phase;
|
||||
Status = NotifyPhaseProc (&NotifyPhaseParams);
|
||||
if (Status != 0) {
|
||||
printk(BIOS_DEBUG, "FSP API NotifyPhase failed for phase %d!\n", Phase);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Board Specific routine before handling over to boot loader.
|
||||
*/
|
||||
#if !defined(__PRE_RAM__)
|
||||
void mainboard_cbmem_post_handling(void)
|
||||
{
|
||||
|
||||
/* Notify FSP for ReadyToBoot */
|
||||
FspNotifyPhase (EnumInitPhaseReadyToBoot);
|
||||
}
|
||||
#endif
|
||||
|
||||
/**
|
||||
This function overrides the default configurations in the UPD data region.
|
||||
|
||||
@param UpdDataRgn A pointer to the UPD_DATA_REGION data strcture.
|
||||
|
||||
@return None
|
||||
**/
|
||||
VOID
|
||||
UpdateFspUpdConfigs (
|
||||
UPD_DATA_REGION *FspUpdRgn
|
||||
)
|
||||
{
|
||||
/* Override any UPD setting if required */
|
||||
|
||||
//
|
||||
// Uncomment the line below to disable LAN device
|
||||
//
|
||||
//FspUpdRgn->PcdEnableLan = 0;
|
||||
|
||||
}
|
||||
Loading…
Reference in New Issue