skylake: clean up SMM region calculations
The TSEG is defined to be from TSEG->BGSM in the host bridge registers. Use those registers at runtime to calculate the correct TSEG size. Lastly, use a few helper macros to make constants more readable. BUG=chrome-os-partner:43522 BRANCH=None TEST=Built, booted, suspended, resumed on glados. Original-Change-Id: I6db424a0057ecfc040a3cd5d99476c2fb8f5d29b Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/290832 Original-Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I6890fa450ce8dc10080321aa1a7580e0adc48ad5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11195 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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@ -51,7 +51,6 @@ struct smm_relocation_params {
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int smm_save_state_in_msrs;
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int smm_save_state_in_msrs;
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};
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};
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#define smm_region_size mmap_region_granluarity
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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int smm_initialize(void);
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int smm_initialize(void);
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void smm_relocate(void);
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void smm_relocate(void);
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@ -25,6 +25,7 @@
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <soc/smm.h>
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#include <soc/smm.h>
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#include <soc/systemagent.h>
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#include <soc/systemagent.h>
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#include <stdlib.h>
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size_t mmap_region_granluarity(void)
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size_t mmap_region_granluarity(void)
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{
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{
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@ -34,24 +35,30 @@ size_t mmap_region_granluarity(void)
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return CONFIG_SMM_TSEG_SIZE;
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return CONFIG_SMM_TSEG_SIZE;
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/* Make it 8MiB by default. */
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/* Make it 8MiB by default. */
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return 8 << 20;
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return 8*MiB;
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}
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}
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static void *smm_region_start(void)
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/* Returns base of requested region encoded in the system agent. */
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static inline uintptr_t system_agent_region_base(size_t reg)
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{
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{
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/*
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/* All regions concerned for have 1 MiB alignment. */
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* SMM base address matches the top of DPR. The DPR register has
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return ALIGN_DOWN(pci_read_config32(SA_DEV_ROOT, reg), 1*MiB);
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* 1 MiB alignment and reports the TOP of the DPR range.
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}
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*/
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uint32_t smm_base = pci_read_config32(SA_DEV_ROOT, DPR);
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static inline uintptr_t smm_region_start(void)
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smm_base = ALIGN_DOWN(smm_base, 1 << 20);
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{
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return (void *)smm_base;
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return system_agent_region_base(TSEG);
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}
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static inline size_t smm_region_size(void)
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{
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return system_agent_region_base(BGSM) - smm_region_start();
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}
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}
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void smm_region(void **start, size_t *size)
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void smm_region(void **start, size_t *size)
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{
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{
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*start = smm_region_start();
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*start = (void *)smm_region_start();
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*size = mmap_region_granluarity();
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*size = smm_region_size();
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}
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}
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void *cbmem_top(void)
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void *cbmem_top(void)
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@ -84,7 +91,7 @@ void *cbmem_top(void)
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* +-------------------------+
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* +-------------------------+
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*/
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*/
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unsigned long top_of_ram = (unsigned long)smm_region_start();
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uintptr_t top_of_ram = smm_region_start();
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/*
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/*
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* Subtract DMA Protected Range size if enabled and align to a multiple
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* Subtract DMA Protected Range size if enabled and align to a multiple
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