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soc/intel/{cannonlake,skylake}: fix PCH_P2SB_EPMASK macro 

The PCH_P2SB_EPMASK macro takes a parameter. Ensure parenthesis
are put around the parameter expansion.

Change-Id: I978e9397036ea3630434982fe4ecd698877fe0d6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/21004
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Aaron Durbin 2017-08-14 12:08:43 -06:00
parent 40b2ae3ff8
commit a045fb9de8
2 changed files with 2 additions and 2 deletions
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2
src/soc/intel/cannonlake/include/soc/p2sb.h
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@ -20,7 +20,7 @@
#define HPTC_ADDR_ENABLE_BIT (1 << 7) #define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0x220 #define PCH_P2SB_EPMASK0 0x220
#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + (mask_number * 4)) #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
#define PCH_P2SB_E0 0xE0 #define PCH_P2SB_E0 0xE0

2
src/soc/intel/skylake/include/soc/p2sb.h
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@ -20,7 +20,7 @@
#define HPTC_ADDR_ENABLE_BIT (1 << 7) #define HPTC_ADDR_ENABLE_BIT (1 << 7)
#define PCH_P2SB_EPMASK0 0xB0 #define PCH_P2SB_EPMASK0 0xB0
#define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + (mask_number * 4)) #define PCH_P2SB_EPMASK(mask_number) (PCH_P2SB_EPMASK0 + ((mask_number) * 4))
#define PCH_P2SB_E0 0xE0 #define PCH_P2SB_E0 0xE0
#define PCH_PWRM_ACPI_TMR_CTL 0xFC #define PCH_PWRM_ACPI_TMR_CTL 0xFC