soc/amd/sabrina: only make the available clock outputs configurable

Sabrina only has 4 PCIe clock outputs with corresponding clock request
pins available, so only make those 4 configurable in devicetree and
disable the rest unconditionally.

TEST=None

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5d34fa680dd20a6eec86cc278c1c901b3231df83
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Felix Held 2022-06-10 21:04:36 +02:00
parent 868282e195
commit a05f518dea
3 changed files with 6 additions and 3 deletions

View File

@ -90,7 +90,7 @@ struct soc_amd_sabrina_config {
GPP_CLK_ON, /* GPP clock always on; default */ GPP_CLK_ON, /* GPP clock always on; default */
GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */ GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
GPP_CLK_OFF, /* GPP clk off */ GPP_CLK_OFF, /* GPP clk off */
} gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; } gpp_clk_config[GPP_CLK_OUTPUT_AVAILABLE];
/* performance policy for the PCIe links: power consumption vs. link speed */ /* performance policy for the PCIe links: power consumption vs. link speed */
enum { enum {

View File

@ -151,9 +151,11 @@ static void gpp_clk_setup(void)
* The remapping of values is done so that the default of the enum used for the * The remapping of values is done so that the default of the enum used for the
* devicetree settings is the clock being enabled, so that a missing devicetree * devicetree settings is the clock being enabled, so that a missing devicetree
* configuration for this will result in an always active clock and not an * configuration for this will result in an always active clock and not an
* inactive PCIe clock output. * inactive PCIe clock output. Only the configuration for the clock outputs
* available on the package is provided via the devicetree; the rest is
* switched off unconditionally.
*/ */
switch (cfg->gpp_clk_config[i]) { switch (i < GPP_CLK_OUTPUT_AVAILABLE ? cfg->gpp_clk_config[i] : GPP_CLK_OFF) {
case GPP_CLK_REQ: case GPP_CLK_REQ:
gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]); gpp_clk_ctl |= GPP_CLK_REQ_EXT(gpp_clk_shift_lut[i]);
break; break;

View File

@ -96,6 +96,7 @@
#define GPP_CLK5_REQ_SHIFT 10 #define GPP_CLK5_REQ_SHIFT 10
#define GPP_CLK6_REQ_SHIFT 12 #define GPP_CLK6_REQ_SHIFT 12
#define GPP_CLK_OUTPUT_COUNT 7 #define GPP_CLK_OUTPUT_COUNT 7
#define GPP_CLK_OUTPUT_AVAILABLE 4
#define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_MASK(clk_shift) (0x3 << (clk_shift))
#define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift)) #define GPP_CLK_REQ_ON(clk_shift) (0x3 << (clk_shift))
#define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift)) #define GPP_CLK_REQ_EXT(clk_shift) (0x1 << (clk_shift))