diff --git a/src/soc/amd/stoneyridge/include/soc/smi.h b/src/soc/amd/stoneyridge/include/soc/smi.h
index 0a865b7496..797f4e8578 100644
--- a/src/soc/amd/stoneyridge/include/soc/smi.h
+++ b/src/soc/amd/stoneyridge/include/soc/smi.h
@@ -200,9 +200,9 @@ struct smi_sources_t {
 };
 
 uint16_t pm_acpi_smi_cmd_port(void);
+void configure_smi(uint8_t smi_num, uint8_t mode);
 void configure_gevent_smi(uint8_t gevent, uint8_t mode, uint8_t level);
 void disable_gevent_smi(uint8_t gevent);
-void enable_acpi_cmd_smi(void);
 
 #ifndef __SMM__
 void enable_smi_generation(void);
diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c
index 833e6e37e6..96e9d6156b 100644
--- a/src/soc/amd/stoneyridge/smi_util.c
+++ b/src/soc/amd/stoneyridge/smi_util.c
@@ -9,7 +9,7 @@
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 
-static void configure_smi(uint8_t smi_num, uint8_t mode)
+void configure_smi(uint8_t smi_num, uint8_t mode)
 {
 	uint8_t reg32_offset, bit_offset;
 	uint32_t reg32;
@@ -69,12 +69,6 @@ void disable_gevent_smi(uint8_t gevent)
 	configure_smi(gevent, SMI_MODE_DISABLE);
 }
 
-/** Enable SMIs on writes to ACPI SMI command port */
-void enable_acpi_cmd_smi(void)
-{
-	configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
-}
-
 uint16_t pm_acpi_smi_cmd_port(void)
 {
 	return pm_read16(PM_ACPI_SMI_CMD);
diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c
index 3356e97752..b947be123f 100644
--- a/src/soc/amd/stoneyridge/southbridge.c
+++ b/src/soc/amd/stoneyridge/southbridge.c
@@ -57,8 +57,9 @@ static void sb_init_acpi_ports(void)
 	pm_write16(PM_CPU_CTRL, ACPI_CPU_CONTROL);
 
 	if (IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)) {
+		/* APMC - SMI Command Port */
 		pm_write16(PM_ACPI_SMI_CMD, APM_CNT);
-		enable_acpi_cmd_smi();
+		configure_smi(SMITYPE_SMI_CMD_PORT, SMI_MODE_SMI);
 	} else {
 		pm_write16(PM_ACPI_SMI_CMD, 0);
 	}