From a0696645b0bfaefbbca08135055213a852949e72 Mon Sep 17 00:00:00 2001 From: Raul E Rangel Date: Tue, 1 Feb 2022 12:16:57 -0700 Subject: [PATCH] mb/google/guybrush: Enable PSP port 80s Let's re-enable PSP post codes when running PSP verstage. The original reason we disabled POST codes was that it was causing problems during eSPI init in bootblock. Since we now init eSPI in PSP verstage, it's safe to re-enable them. We can now see post codes during S0i3 enter and exit. This will help when debugging resume or suspend hangs. Port 80 writes on suspend: ef000020 ef00ed00 ef00ed01 ef000021 <--new Port 80 writes on resume: 05 eea80025 eea90000 eea90100 eea90200 eea50000 eeae0000 eeae0004 eeaf0000 eeb00000 eec00000 eec00100 eec10000 eec40000 eec40500 eec40200 eefc0000 eefc0100 eec50000 ea00e0fc ea00abc1 ea00e60b ea00e60c ea00abe1 ea00abe2 ea00abe4 ea00abe5 ea00abeb ea00abec ea00abed ea00abee ea00abef ea00e10f ea00e098 ea00e099 ea00abf0 ea00abf2 ea00e10e ea00e60c ea00e101 ea00e090 ea00e091 ea00e098 ea00e099 ea00e098 ea00e099 ea00e100 ea00e60c ea00e0b0 ea00e0b4 ea00e0b7 ea00e60c ea00e0c2 ea00e0c4 ea00e0d3 ea00e60c ea00e10d ea00e0c1 ea00e10c ea00e60c ea00e0c4 e000 eec60000 eec20000 eec20800 b40000 eeb50000 eefc0000 eefc0300 ee070000 eed90000 eed90700 eeda0600 eedd0000 eecb0000 eecf0000 eecf0200 eee30000 eee30900 eee40000 ef000025 BUG=b:215425753 TEST=Boot/suspend/resume guybrush and verify post codes are printed Signed-off-by: Raul E Rangel Change-Id: Ie759f66be2b8ffac19145491a227752d4762a5b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/61535 Tested-by: build bot (Jenkins) Reviewed-by: Rob Barnes Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/guybrush/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/guybrush/Kconfig b/src/mainboard/google/guybrush/Kconfig index b2ce989bf7..43cbddedc6 100644 --- a/src/mainboard/google/guybrush/Kconfig +++ b/src/mainboard/google/guybrush/Kconfig @@ -41,7 +41,7 @@ config BOARD_SPECIFIC_OPTIONS select PCIEXP_CLK_PM select PCIEXP_COMMON_CLOCK select PCIEXP_L1_SUB_STATE - select PSP_DISABLE_POSTCODES + select PSP_DISABLE_POSTCODES if !VBOOT_STARTS_BEFORE_BOOTBLOCK select PSP_S0I3_RESUME_VERSTAGE if VBOOT_STARTS_BEFORE_BOOTBLOCK select SOC_AMD_CEZANNE select SOC_AMD_COMMON_BLOCK_GRAPHICS_ATIF