This patch adds the ECS P6IWP-Fe board to coreboot.
Signed-off-by: Anders Jenbo <anders@jenbo.dk> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5623 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Anders Jenbo
Stefan Reinauer
parent
bd8d7eed2d
commit
a06f950c27
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@ -40,6 +40,8 @@ config VENDOR_DIGITAL_LOGIC
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bool "DIGITAL-LOGIC"
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bool "DIGITAL-LOGIC"
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config VENDOR_EAGLELION
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config VENDOR_EAGLELION
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bool "EagleLion"
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bool "EagleLion"
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config VENDOR_ECS
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bool "ECS"
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config VENDOR_EMULATION
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config VENDOR_EMULATION
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bool "Emulation"
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bool "Emulation"
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config VENDOR_GETAC
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config VENDOR_GETAC
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@ -201,6 +203,11 @@ config MAINBOARD_VENDOR
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default "EagleLion"
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default "EagleLion"
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depends on VENDOR_EAGLELION
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depends on VENDOR_EAGLELION
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config MAINBOARD_VENDOR
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string
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default "ECS"
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depends on VENDOR_ECS
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config MAINBOARD_VENDOR
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config MAINBOARD_VENDOR
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string
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string
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default "Emulation"
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default "Emulation"
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@ -424,6 +431,7 @@ source "src/mainboard/compaq/Kconfig"
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source "src/mainboard/dell/Kconfig"
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source "src/mainboard/dell/Kconfig"
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source "src/mainboard/digitallogic/Kconfig"
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source "src/mainboard/digitallogic/Kconfig"
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source "src/mainboard/eaglelion/Kconfig"
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source "src/mainboard/eaglelion/Kconfig"
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source "src/mainboard/ecs/Kconfig"
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source "src/mainboard/emulation/Kconfig"
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source "src/mainboard/emulation/Kconfig"
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source "src/mainboard/getac/Kconfig"
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source "src/mainboard/getac/Kconfig"
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source "src/mainboard/gigabyte/Kconfig"
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source "src/mainboard/gigabyte/Kconfig"
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@ -0,0 +1,28 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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choice
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prompt "Mainboard model"
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depends on VENDOR_ECS
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source "src/mainboard/ecs/p6iwp-fe/Kconfig"
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endchoice
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@ -0,0 +1,52 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config BOARD_ECS_P6IWP_FE
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bool "P6IWP-FE"
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select ARCH_X86
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select CPU_INTEL_SOCKET_PGA370
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select NORTHBRIDGE_INTEL_I82810
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select SOUTHBRIDGE_INTEL_I82801AX
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select SUPERIO_ITE_IT8712F
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select ROMCC
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select HAVE_PIRQ_TABLE
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select UDELAY_TSC
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select BOARD_ROMSIZE_KB_512
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config MAINBOARD_DIR
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string
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default ecs/p6iwp-fe
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depends on BOARD_ECS_P6IWP_FE
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config MAINBOARD_PART_NUMBER
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string
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default "P6IWP-FE"
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depends on BOARD_ECS_P6IWP_FE
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config HAVE_OPTION_TABLE
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bool
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default n
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depends on BOARD_ECS_P6IWP_FE
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config IRQ_SLOT_COUNT
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int
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default 10
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depends on BOARD_ECS_P6IWP_FE
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@ -0,0 +1,22 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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extern struct chip_operations mainboard_ops;
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struct mainboard_config {};
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@ -0,0 +1,66 @@
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chip northbridge/intel/i82810 # Northbridge
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device lapic_cluster 0 on # APIC cluster
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chip cpu/intel/socket_PGA370 # CPU
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device lapic 0 on end # APIC
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end
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end
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device pci_domain 0 on # PCI domain
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device pci 0.0 on end # Graphics Memory Controller Hub (GMCH)
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device pci 1.0 on end # Chipset Graphics Controller (CGC)
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chip southbridge/intel/i82801ax # Southbridge
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register "ide0_enable" = "1"
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register "ide1_enable" = "1"
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device pci 1e.0 on end # PCI bridge
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device pci 1f.0 on # ISA bridge
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chip superio/ite/it8712f # Super I/O
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device pnp 2e.0 off # Floppy
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io 0x60 = 0x3f0
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irq 0x70 = 6
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drq 0x74 = 2
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end
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device pnp 2e.1 on # Com1
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io 0x60 = 0x3f8
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irq 0x70 = 4
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end
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device pnp 2e.2 on # Com2
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io 0x60 = 0x2f8
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irq 0x70 = 3
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end
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device pnp 2e.3 on # Parallel port
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io 0x60 = 0x378
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irq 0x70 = 7
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end
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device pnp 2e.4 on # EC
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io 0x60 = 0x290
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io 0x62 = 0x230
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irq 0x70 = 9
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end
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device pnp 2e.5 on # PS/2 keyboard
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io 0x60 = 0x60
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io 0x62 = 0x64
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irq 0x70 = 1
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end
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device pnp 2e.6 on # PS/2 mouse
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irq 0x70 = 12
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end
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device pnp 2e.7 on # GPIO
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io 0x62 = 0x1220
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io 0x64 = 0x1200
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end
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device pnp 2e.8 off # MIDI
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io 0x60 = 0x300
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irq 0x70 = 9
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end
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device pnp 2e.9 off # Game port
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io 0x60 = 0x220
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end
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device pnp 2e.a off end # CIR
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end
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end
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device pci 1f.1 on end # IDE
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device pci 1f.2 on end # USB
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device pci 1f.3 on end # SMBus
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end
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end
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end
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@ -0,0 +1,56 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/pirq_routing.h>
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const struct irq_routing_table intel_irq_routing_table = {
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PIRQ_SIGNATURE, /* u32 signature */
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PIRQ_VERSION, /* u16 version */
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32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* Max. number of devices on the bus */
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0x00, /* Interrupt router bus */
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(0x1f << 3) | 0x0, /* Interrupt router dev */
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0x1c00, /* IRQs devoted exclusively to PCI usage */
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0x8086, /* Vendor */
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0x7000, /* Device */
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0, /* Miniport */
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{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
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0x7, /* Checksum (has to be set to some value that
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* would give 0 after the sum of all bytes
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* for this structure (including checksum).
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*/
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{
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/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
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{0x00, (0x1e << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x1, 0x0},
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{0x00, (0x10 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x2, 0x0},
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{0x01, (0x04 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x3, 0x0},
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{0x01, (0x05 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x4, 0x0},
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{0x01, (0x0a << 3) | 0x0, {{0x63, 0xdeb8}, {0x62, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x5, 0x0},
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{0x01, (0x07 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x6, 0x0},
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{0x01, (0x08 << 3) | 0x0, {{0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}}, 0x7, 0x0},
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{0x01, (0x09 << 3) | 0x0, {{0x62, 0xdeb8}, {0x63, 0xdeb8}, {0x60, 0xdeb8}, {0x61, 0xdeb8}}, 0x8, 0x0},
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{0x00, (0x01 << 3) | 0x0, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
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{0x00, (0x1f << 3) | 0x1, {{0x60, 0xdeb8}, {0x61, 0xdeb8}, {0x62, 0xdeb8}, {0x63, 0xdeb8}}, 0x0, 0x0},
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}
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};
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unsigned long write_pirq_routing_table(unsigned long addr)
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{
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return copy_pirq_routing_table(addr);
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}
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@ -0,0 +1,26 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
|
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <device/device.h>
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#include "chip.h"
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struct chip_operations mainboard_ops = {
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CHIP_NAME("ECS P6IWP-Fe Mainboard")
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};
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@ -0,0 +1,72 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
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* Copyright (C) 2010 Anders Jenbo <anders@jenbo.dk>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include <device/pci_def.h>
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#include <arch/io.h>
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#include <device/pnp_def.h>
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#include <arch/romcc_io.h>
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#include <arch/hlt.h>
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#include <console/console.h>
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#include "lib/ramtest.c"
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#include "southbridge/intel/i82801ax/i82801ax_early_smbus.c"
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#include "northbridge/intel/i82810/raminit.h"
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#include "lib/debug.c"
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#include "pc80/udelay_io.c"
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#include "lib/delay.c"
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#include "cpu/x86/mtrr/earlymtrr.c"
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#include "cpu/x86/bist.h"
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#include "superio/ite/it8712f/it8712f_early_serial.c"
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static inline int spd_read_byte(unsigned int device, unsigned int address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/intel/i82810/raminit.c"
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#include "northbridge/intel/i82810/debug.c"
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||||||
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/* Early mainboard specific GPIO setup. */
|
||||||
|
static void mb_gpio_init(void)
|
||||||
|
{
|
||||||
|
}
|
||||||
|
|
||||||
|
static void main(unsigned long bist)
|
||||||
|
{
|
||||||
|
if (bist == 0)
|
||||||
|
early_mtrr_init();
|
||||||
|
|
||||||
|
it8712f_24mhz_clkin();
|
||||||
|
it8712f_enable_serial(0, CONFIG_TTYS0_BASE); // Does not use its 1st parameter
|
||||||
|
mb_gpio_init();
|
||||||
|
uart_init();
|
||||||
|
console_init();
|
||||||
|
report_bist_failure(bist);
|
||||||
|
enable_smbus();
|
||||||
|
dump_spd_registers();
|
||||||
|
sdram_set_registers();
|
||||||
|
sdram_set_spd_registers();
|
||||||
|
sdram_enable();
|
||||||
|
dump_spd_registers();
|
||||||
|
/* ram_check(0, 640 * 1024); */
|
||||||
|
}
|
||||||
|
|
||||||
Loading…
Reference in New Issue