soc/intel/cannonlake: Make correct IRQ mapping for CNL SA and PCH PCI devices
This patch provides option for PCI IRQ mapping in both PIC and APIC mode. TEST=Build and Boot on CNL RVP. Change-Id: Ie26750ac9dc2ce940b0c116085c041de439075df Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/28799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
This commit is contained in:
Subrata Banik
Duncan Laurie
parent
50cdce9575
commit
a0729899d7
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@ -0,0 +1,282 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2018 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* PIRQ routing control is in PCR ITSS region.
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*
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* Due to what appears to be an ACPI interpreter bug we do not use
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* the PCRB() method here as it may not be defined yet because the method
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* definiton depends on the order of the include files in pch.asl.
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*
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* https://bugs.acpica.org/show_bug.cgi?id=1201
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*/
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OperationRegion (ITSS, SystemMemory,
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Add (PCR_ITSS_PIRQA_ROUT,
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Add (CONFIG_PCR_BASE_ADDRESS,
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ShiftLeft (PID_ITSS, PCR_PORTID_SHIFT))), 8)
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Field (ITSS, ByteAcc, NoLock, Preserve)
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{
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PIRA, 8, /* PIRQA Routing Control */
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PIRB, 8, /* PIRQB Routing Control */
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PIRC, 8, /* PIRQC Routing Control */
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PIRD, 8, /* PIRQD Routing Control */
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PIRE, 8, /* PIRQE Routing Control */
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PIRF, 8, /* PIRQF Routing Control */
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PIRG, 8, /* PIRQG Routing Control */
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PIRH, 8, /* PIRQH Routing Control */
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}
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Name (IREN, 0x80) /* Interrupt Routing Enable */
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Name (IREM, 0x0f) /* Interrupt Routing Mask */
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Device (LNKA)
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{
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Name (_HID, EISAID ("PNP0C0F"))
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Name (_UID, 1)
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Method (_CRS, 0, Serialized)
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{
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Name (RTLA, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared) {11}
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})
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CreateWordField (RTLA, 1, IRQ0)
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Store (Zero, IRQ0)
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/* Set the bit from PIRQ Routing Register */
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ShiftLeft (1, And (^^PIRA, ^^IREM), IRQ0)
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Return (RTLA)
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}
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Method (_STA, 0, Serialized)
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{
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If (And (^^PIRA, ^^IREN)) {
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Return (0x9)
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} Else {
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Return (0xb)
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}
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}
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}
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Device (LNKB)
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{
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Name (_HID, EISAID ("PNP0C0F"))
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Name (_UID, 2)
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Method (_CRS, 0, Serialized)
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{
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Name (RTLB, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared) {10}
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})
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CreateWordField (RTLB, 1, IRQ0)
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Store (Zero, IRQ0)
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/* Set the bit from PIRQ Routing Register */
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ShiftLeft (1, And (^^PIRB, ^^IREM), IRQ0)
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Return (RTLB)
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}
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Method (_STA, 0, Serialized)
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{
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If (And (^^PIRB, ^^IREN)) {
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Return (0x9)
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} Else {
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Return (0xb)
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}
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}
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}
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Device (LNKC)
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{
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Name (_HID, EISAID ("PNP0C0F"))
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Name (_UID, 3)
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Method (_CRS, 0, Serialized)
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{
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Name (RTLC, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared) {11}
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})
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CreateWordField (RTLC, 1, IRQ0)
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Store (Zero, IRQ0)
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/* Set the bit from PIRQ Routing Register */
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ShiftLeft (1, And (^^PIRC, ^^IREM), IRQ0)
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Return (RTLC)
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}
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Method (_STA, 0, Serialized)
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{
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If (And (^^PIRC, ^^IREN)) {
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Return (0x9)
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} Else {
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Return (0xb)
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}
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}
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}
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Device (LNKD)
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{
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Name (_HID, EISAID ("PNP0C0F"))
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Name (_UID, 4)
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Method (_CRS, 0, Serialized)
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{
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Name (RTLD, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared) {11}
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})
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CreateWordField (RTLD, 1, IRQ0)
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Store (Zero, IRQ0)
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/* Set the bit from PIRQ Routing Register */
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ShiftLeft (1, And (^^PIRD, ^^IREM), IRQ0)
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Return (RTLD)
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}
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Method (_STA, 0, Serialized)
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{
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If (And (^^PIRD, ^^IREN)) {
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Return (0x9)
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} Else {
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Return (0xb)
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}
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}
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}
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Device (LNKE)
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{
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Name (_HID, EISAID ("PNP0C0F"))
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Name (_UID, 5)
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Method (_CRS, 0, Serialized)
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{
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Name (RTLE, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared) {11}
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})
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CreateWordField (RTLE, 1, IRQ0)
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Store (Zero, IRQ0)
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/* Set the bit from PIRQ Routing Register */
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ShiftLeft (1, And (^^PIRE, ^^IREM), IRQ0)
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Return (RTLE)
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}
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Method (_STA, 0, Serialized)
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{
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If (And (^^PIRE, ^^IREN)) {
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Return (0x9)
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} Else {
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Return (0xb)
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}
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}
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}
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Device (LNKF)
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{
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Name (_HID, EISAID ("PNP0C0F"))
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Name (_UID, 6)
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Method (_CRS, 0, Serialized)
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{
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Name (RTLF, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared) {11}
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})
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CreateWordField (RTLF, 1, IRQ0)
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Store (Zero, IRQ0)
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/* Set the bit from PIRQ Routing Register */
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ShiftLeft (1, And (^^PIRF, ^^IREM), IRQ0)
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Return (RTLF)
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}
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Method (_STA, 0, Serialized)
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{
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If (And (^^PIRF, ^^IREN)) {
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Return (0x9)
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} Else {
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Return (0xb)
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}
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}
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}
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Device (LNKG)
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{
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Name (_HID, EISAID ("PNP0C0F"))
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Name (_UID, 7)
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Method (_CRS, 0, Serialized)
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{
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Name (RTLG, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared) {11}
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})
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CreateWordField (RTLG, 1, IRQ0)
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Store (Zero, IRQ0)
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/* Set the bit from PIRQ Routing Register */
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ShiftLeft (1, And (^^PIRG, ^^IREM), IRQ0)
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Return (RTLG)
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}
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Method (_STA, 0, Serialized)
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{
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If (And (^^PIRG, ^^IREN)) {
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Return (0x9)
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} Else {
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Return (0xb)
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}
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}
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}
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Device (LNKH)
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{
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Name (_HID, EISAID ("PNP0C0F"))
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Name (_UID, 8)
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Method (_CRS, 0, Serialized)
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{
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Name (RTLH, ResourceTemplate ()
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{
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IRQ (Level, ActiveLow, Shared) {11}
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})
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CreateWordField (RTLH, 1, IRQ0)
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Store (Zero, IRQ0)
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/* Set the bit from PIRQ Routing Register */
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ShiftLeft (1, And (^^PIRH, ^^IREM), IRQ0)
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Return (RTLH)
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}
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Method (_STA, 0, Serialized)
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{
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If (And (^^PIRH, ^^IREN)) {
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Return (0x9)
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} Else {
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Return (0xb)
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}
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}
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}
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@ -1,7 +1,7 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2017 Intel Corp.
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* Copyright (C) 2017-2018 Intel Corp.
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* (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
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*
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* This program is free software; you can redistribute it and/or modify
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@ -15,85 +15,127 @@
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* GNU General Public License for more details.
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*/
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Method(_PRT)
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#include <soc/irq.h>
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Name (PICP, Package () {
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/* PCI Bridge */
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/* cAVS, SMBus, GbE, Nothpeak */
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Package(){0x001FFFFF, 0, 0, cAVS_INTA_IRQ },
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Package(){0x001FFFFF, 1, 0, SMBUS_INTB_IRQ },
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Package(){0x001FFFFF, 2, 0, GbE_INTC_IRQ },
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Package(){0x001FFFFF, 3, 0, TRACE_HUB_INTD_IRQ },
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/* SerialIo and SCS */
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Package(){0x001EFFFF, 0, 0, LPSS_UART0_IRQ },
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Package(){0x001EFFFF, 1, 0, LPSS_UART1_IRQ },
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Package(){0x001EFFFF, 2, 0, LPSS_SPI0_IRQ },
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Package(){0x001EFFFF, 3, 0, LPSS_SPI1_IRQ },
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/* PCI Express Port 9-16 */
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Package(){0x001DFFFF, 0, 0, PCIE_9_IRQ },
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Package(){0x001DFFFF, 1, 0, PCIE_10_IRQ },
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Package(){0x001DFFFF, 2, 0, PCIE_11_IRQ },
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Package(){0x001DFFFF, 3, 0, PCIE_12_IRQ },
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/* PCI Express Port 1-8 */
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Package(){0x001CFFFF, 0, 0, PCIE_1_IRQ },
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Package(){0x001CFFFF, 1, 0, PCIE_2_IRQ },
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Package(){0x001CFFFF, 2, 0, PCIE_3_IRQ },
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Package(){0x001CFFFF, 3, 0, PCIE_4_IRQ },
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/* eMMC */
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Package(){0x001AFFFF, 0, 0, eMMC_IRQ },
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/* SerialIo */
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Package(){0x0019FFFF, 0, 0, LPSS_I2C4_IRQ },
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Package(){0x0019FFFF, 1, 0, LPSS_I2C5_IRQ },
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Package(){0x0019FFFF, 2, 0, LPSS_UART2_IRQ },
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/* SATA controller */
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Package(){0x0017FFFF, 0, 0, SATA_IRQ },
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/* CSME (HECI, IDE-R, Keyboard and Text redirection */
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Package(){0x0016FFFF, 0, 0, HECI_1_IRQ },
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Package(){0x0016FFFF, 1, 0, HECI_2_IRQ },
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Package(){0x0016FFFF, 2, 0, IDER_IRQ },
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Package(){0x0016FFFF, 3, 0, KT_IRQ },
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/* SerialIo */
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Package(){0x0015FFFF, 0, 0, LPSS_I2C0_IRQ },
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Package(){0x0015FFFF, 1, 0, LPSS_I2C1_IRQ },
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Package(){0x0015FFFF, 2, 0, LPSS_I2C2_IRQ },
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Package(){0x0015FFFF, 3, 0, LPSS_I2C3_IRQ },
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/* D20: xHCI, OTG, SRAM, CNVi WiFi */
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Package(){0x0014FFFF, 0, 0, XHCI_IRQ },
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Package(){0x0014FFFF, 1, 0, OTG_IRQ },
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Package(){0x0014FFFF, 2, 0, PMC_SRAM_IRQ },
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Package(){0x0014FFFF, 3, 0, CNViWIFI_IRQ },
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/* Integrated Sensor Hub */
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Package(){0x0013FFFF, 0, 0, ISH_IRQ },
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/* Thermal */
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Package(){0x0012FFFF, 0, 0, THERMAL_IRQ },
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/* Host Bridge */
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/* Root Port D1F0 */
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Package(){0x0001FFFF, 0, 0, PEG_RP_INTA_IRQ },
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Package(){0x0001FFFF, 1, 0, PEG_RP_INTB_IRQ },
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Package(){0x0001FFFF, 2, 0, PEG_RP_INTC_IRQ },
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Package(){0x0001FFFF, 3, 0, PEG_RP_INTD_IRQ },
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/* SA IGFX Device */
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Package(){0x0002FFFF, 0, 0, IGFX_IRQ },
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/* SA Thermal Device */
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Package(){0x0004FFFF, 0, 0, SA_THERMAL_IRQ },
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/* SA IPU Device */
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Package(){0x0005FFFF, 0, 0, IPU_IRQ },
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/* SA GNA Device */
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Package(){0x0008FFFF, 0, 0, GNA_IRQ },
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})
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Name (PICN, Package () {
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/* D31: cAVS, SMBus, GbE, Nothpeak */
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Package () { 0x001FFFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x001FFFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x001FFFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x001FFFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D32: Can't use PIC*/
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/* D29: PCI Express Port 9-16 */
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Package () { 0x001DFFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x001DFFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x001DFFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x001DFFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D28: PCI Express Port 1-8 */
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Package () { 0x001CFFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x001CFFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x001CFFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x001CFFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D25: Can't use PIC*/
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/* D23 */
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Package () { 0x0017FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* D22: CSME (HECI, IDE-R, KT redirection */
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Package () { 0x0016FFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0016FFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0016FFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0016FFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D21: Can't use PIC*/
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/* D20: xHCI, OTG, SRAM, CNVi WiFi */
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Package () { 0x0014FFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0014FFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0014FFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0014FFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* D19: Can't use PIC*/
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/* Thermal */
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Package () { 0x0012FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* P.E.G. Root Port D1F0 */
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Package () { 0x0001FFFF, 0, \_SB.PCI0.LNKA, 0 },
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Package () { 0x0001FFFF, 1, \_SB.PCI0.LNKB, 0 },
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Package () { 0x0001FFFF, 2, \_SB.PCI0.LNKC, 0 },
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Package () { 0x0001FFFF, 3, \_SB.PCI0.LNKD, 0 },
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/* SA IGFX Device */
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Package () { 0x0002FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* SA Thermal Device */
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Package () { 0x0004FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* SA IPU Device */
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Package () { 0x0005FFFF, 0, \_SB.PCI0.LNKA, 0 },
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/* SA GNA Device */
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Package () { 0x0008FFFF, 0, \_SB.PCI0.LNKA, 0 },
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})
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Method (_PRT)
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{
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Return(Package() {
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// PCI Bridge
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// cAVS, SMBus, GbE, Nothpeak
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Package(){0x001FFFFF, 0, 0, 16 },
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Package(){0x001FFFFF, 1, 0, 17 },
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Package(){0x001FFFFF, 2, 0, 18 },
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Package(){0x001FFFFF, 3, 0, 19 },
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// SerialIo and SCS
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Package(){0x001EFFFF, 0, 0, 20 },
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Package(){0x001EFFFF, 1, 0, 21 },
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Package(){0x001EFFFF, 2, 0, 22 },
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Package(){0x001EFFFF, 3, 0, 23 },
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// PCI Express Port 9-16
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Package(){0x001DFFFF, 0, 0, 16 },
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Package(){0x001DFFFF, 1, 0, 17 },
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Package(){0x001DFFFF, 2, 0, 18 },
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Package(){0x001DFFFF, 3, 0, 19 },
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// PCI Express Port 1-8
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Package(){0x001CFFFF, 0, 0, 16 },
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Package(){0x001CFFFF, 1, 0, 17 },
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Package(){0x001CFFFF, 2, 0, 18 },
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Package(){0x001CFFFF, 3, 0, 19 },
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// PCI Express Port 17-20
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Package(){0x001BFFFF, 0, 0, 16 },
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Package(){0x001BFFFF, 1, 0, 17 },
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Package(){0x001BFFFF, 2, 0, 18 },
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Package(){0x001BFFFF, 3, 0, 19 },
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// eMMC
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Package(){0x001AFFFF, 0, 0, 16 },
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Package(){0x001AFFFF, 1, 0, 17 },
|
||||
Package(){0x001AFFFF, 2, 0, 18 },
|
||||
Package(){0x001AFFFF, 3, 0, 19 },
|
||||
// SerialIo
|
||||
Package(){0x0019FFFF, 0, 0, 32 },
|
||||
Package(){0x0019FFFF, 1, 0, 33 },
|
||||
Package(){0x0019FFFF, 2, 0, 34 },
|
||||
// SATA controller
|
||||
Package(){0x0017FFFF, 0, 0, 16 },
|
||||
// CSME (HECI, IDE-R, Keyboard and Text redirection
|
||||
Package(){0x0016FFFF, 0, 0, 16 },
|
||||
Package(){0x0016FFFF, 1, 0, 17 },
|
||||
Package(){0x0016FFFF, 2, 0, 18 },
|
||||
Package(){0x0016FFFF, 3, 0, 19 },
|
||||
// SerialIo
|
||||
Package(){0x0015FFFF, 0, 0, 16 },
|
||||
Package(){0x0015FFFF, 1, 0, 17 },
|
||||
Package(){0x0015FFFF, 2, 0, 18 },
|
||||
Package(){0x0015FFFF, 3, 0, 19 },
|
||||
// CNL: D20: xHCI, OTG, CNVi WiFi, SDcard
|
||||
Package(){0x0014FFFF, 0, 0, 16 },
|
||||
Package(){0x0014FFFF, 1, 0, 17 },
|
||||
Package(){0x0014FFFF, 2, 0, 18 },
|
||||
Package(){0x0014FFFF, 3, 0, 19 },
|
||||
// Integrated Sensor Hub
|
||||
Package(){0x0013FFFF, 0, 0, 20 },
|
||||
// Thermal, UFS, SerialIo SPI 2
|
||||
Package(){0x0012FFFF, 0, 0, 16 },
|
||||
Package(){0x0012FFFF, 1, 0, 24 },
|
||||
Package(){0x0012FFFF, 2, 0, 18 },
|
||||
Package(){0x0012FFFF, 3, 0, 19 },
|
||||
|
||||
// Host Bridge
|
||||
// Root Port D1F0
|
||||
Package(){0x0001FFFF, 0, 0, 16 },
|
||||
Package(){0x0001FFFF, 1, 0, 17 },
|
||||
Package(){0x0001FFFF, 2, 0, 18 },
|
||||
Package(){0x0001FFFF, 3, 0, 19 },
|
||||
// Root Port D1F1
|
||||
// Root Port D1F2
|
||||
// IGFX Device
|
||||
Package(){0x0002FFFF, 0, 0, 16 },
|
||||
// Thermal Device
|
||||
Package(){0x0004FFFF, 0, 0, 16 },
|
||||
// IPU Device
|
||||
Package(){0x0005FFFF, 0, 0, 16 },
|
||||
// GNA Device
|
||||
Package(){0x0008FFFF, 0, 0, 16 },
|
||||
})
|
||||
If (PICM) {
|
||||
Return (^PICP)
|
||||
} Else {
|
||||
Return (^PICN)
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -15,6 +15,13 @@
|
|||
* GNU General Public License for more details.
|
||||
*/
|
||||
|
||||
#include <intelblocks/itss.h>
|
||||
#include <intelblocks/pcr.h>
|
||||
#include <soc/itss.h>
|
||||
#include <soc/pcr_ids.h>
|
||||
|
||||
/* Interrupt Routing */
|
||||
#include "irqlinks.asl"
|
||||
|
||||
/* PCI IRQ assignment */
|
||||
#include "pci_irqs.asl"
|
||||
|
|
|
|||
|
|
@ -87,8 +87,9 @@
|
|||
|
||||
#define XHCI_IRQ 16
|
||||
#define OTG_IRQ 17
|
||||
#define THRMAL_IRQ 16
|
||||
#define CNViWIFI_IRQ 16
|
||||
#define PMC_SRAM_IRQ 18
|
||||
#define THERMAL_IRQ 16
|
||||
#define CNViWIFI_IRQ 19
|
||||
#define UFS_IRQ 16
|
||||
#define CIO_INTA_IRQ 16
|
||||
#define CIO_INTD_IRQ 19
|
||||
|
|
@ -101,6 +102,6 @@
|
|||
|
||||
#define IGFX_IRQ 16
|
||||
#define SA_THERMAL_IRQ 16
|
||||
#define SKYCAM_IRQ 16
|
||||
#define GMM_IRQ 16
|
||||
#define IPU_IRQ 16
|
||||
#define GNA_IRQ 16
|
||||
#endif /* _SOC_IRQ_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue