Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-31
Creator: Yinghai Lu <yhlu@tyan.com> nvidia onboard lan support git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1947 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -164,14 +164,14 @@ static void ck804_early_setup(void)
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RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
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RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009000,
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RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
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RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
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RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 2, 0xac), 0xffffff00, 0x00000000,
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#if CK804_NUM > 1
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RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009880,
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RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0x8c), 0xffff0000, 0x00009000,
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RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0x90), 0xffff000f, 0x000074a0,
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RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 2, 0xa0), 0xfffff0ff, 0x00000a00,
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#endif
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@ -286,6 +286,7 @@ static void ck804_early_setup(void)
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
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RES_PORT_IO_8, SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
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RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
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#endif
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#if CK804_USE_ACI == 1
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@ -304,6 +305,7 @@ static void ck804_early_setup(void)
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RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+19, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
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RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(0<<0)),
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RES_PORT_IO_8, CK804B_SYSCTRL_IO_BASE + 0xc0+ 3, ~(0xff), ((0<<4)|(1<<2)|(1<<0)),
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RES_PCI_IO, PCI_ADDR(CK804B_BUSN, CK804_DEVN_BASE+1 , 0, 0xe4), ~(1<<23), (1<<23),
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#endif
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#endif
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@ -21,6 +21,17 @@ static void nic_init(struct device *dev)
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static uint32_t nic_index = 0;
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uint8_t *base;
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struct resource *res;
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res = find_resource(dev, 0x10);
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base = res->base;
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#define NvRegPhyInterface 0xC0
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#define PHY_RGMII 0x10000000
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writel(PHY_RGMII, base + NvRegPhyInterface);
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old = dword = pci_read_config32(dev, 0x30);
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dword &= ~(0xf);
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