mb/google/octopus: I2C clock tuning for meep
Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the frequency does not exceed 400KHz. BUG=b:117298114 TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency under 400 KHz Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/29021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
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@ -1,5 +1,46 @@
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chip soc/intel/apollolake
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# Intel Common SoC Config
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#+-------------------+---------------------------+
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#| Field | Value |
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#+-------------------+---------------------------+
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#| GSPI0 | cr50 TPM. Early init is |
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#| | required to set up a BAR |
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#| | for TPM communication |
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#| | before memory is up |
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#| I2C0 | Digitizer |
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#| I2C5 | Audio |
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#| I2C6 | Trackpad |
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#| I2C7 | Touchscreen |
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#+-------------------+---------------------------+
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register "common_soc_config" = "{
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.gspi[0] = {
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.speed_mhz = 1,
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.early_init = 1,
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},
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.i2c[0] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 120,
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.fall_time_ns = 30,
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},
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.i2c[5] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 104,
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.fall_time_ns = 52,
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},
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.i2c[6] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 66,
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.fall_time_ns = 90,
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.data_hold_time_ns = 350,
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},
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.i2c[7] = {
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.speed = I2C_SPEED_FAST,
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.rise_time_ns = 44,
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.fall_time_ns = 90,
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},
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}"
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device domain 0 on
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device pci 16.0 on
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chip drivers/i2c/hid
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