mb/google/octopus: I2C clock tuning for meep

Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.

BUG=b:117298114
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz

Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/mainboard/google/octopus/variants/meep/overridetree.cb

@@ -1,5 +1,46 @@
 chip soc/intel/apollolake
 
+	# Intel Common SoC Config
+	#+-------------------+---------------------------+
+	#| Field             |  Value                    |
+	#+-------------------+---------------------------+
+	#| GSPI0             | cr50 TPM. Early init is   |
+	#|                   | required to set up a BAR  |
+	#|                   | for TPM communication     |
+	#|                   | before memory is up       |
+	#| I2C0              | Digitizer                 |
+	#| I2C5              | Audio                     |
+	#| I2C6              | Trackpad                  |
+	#| I2C7              | Touchscreen               |
+	#+-------------------+---------------------------+
+	register "common_soc_config" = "{
+		.gspi[0] = {
+			.speed_mhz = 1,
+			.early_init = 1,
+		},
+		.i2c[0] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 120,
+			.fall_time_ns = 30,
+		},
+		.i2c[5] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 104,
+			.fall_time_ns = 52,
+		},
+		.i2c[6] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 66,
+			.fall_time_ns = 90,
+			.data_hold_time_ns = 350,
+		},
+		.i2c[7] = {
+			.speed = I2C_SPEED_FAST,
+			.rise_time_ns = 44,
+			.fall_time_ns = 90,
+		},
+	}"
+
 	device domain 0 on
 		device pci 16.0 on
 			chip drivers/i2c/hid