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rambi: align gpu pipea settings with the VBIOS 

In the normal mode case these settings aren't overwritten by
the VBIOS because the VBIOS does not run. Therefore, the settings
need to align with what the VBIOS programs so that there is a
consistent panel power sequencing.

BUG=chrome-os-partner:28267
BRANCH=baytrail
TEST=Built and booted. Noted settings set by firmware for both dev
     and normal mode match.

Original-Change-Id: Iccf65e2a6bce6859fd7cb0f466d4b44d654523ce
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/196822
Original-Reviewed-by: Marc Jones <marc.jones@se-eng.com>
(cherry picked from commit 12999018f2b08df0c3b9cdac1f16e9c4517ea803)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: Idf1a701ffcb1c990cec2ca1ccca24cc0d26fabbf
Reviewed-on: http://review.coreboot.org/7846
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Aaron Durbin 2014-04-24 11:43:00 -05:00 committed by Marc Jones
parent f2612a1061
commit a081305729
1 changed files with 3 additions and 3 deletions
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6
src/mainboard/google/rambi/devicetree.cb
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@ -41,9 +41,9 @@ chip soc/intel/baytrail
# Enable PIPEA as DP_C # Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "5" # 400ms register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "2000" # 200ms register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "10" # 1ms register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms register "gpu_pipea_light_off_delay" = "2000" # 200ms